公开(公告)号：US11437307B2

公开(公告)日：2022-09-06

申请号：US16949695

申请日：2020-11-11

Applicant: QUALCOMM Incorporated

Inventor： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

公开(公告)号：US10916494B2

公开(公告)日：2021-02-09

申请号：US16453803

申请日：2019-06-26

Applicant: QUALCOMM Incorporated

Inventor： Abdolreza Langari ,  Yuan Li ,  Shrestha Ganguly ,  Terence Cheung ,  Ching-Liou Huang ,  Hui Wang

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.

公开(公告)号：US12300655B2

公开(公告)日：2025-05-13

申请号：US18303345

申请日：2023-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram ,  Abdolreza Langari

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

公开(公告)号：US11670614B2

公开(公告)日：2023-06-06

申请号：US17061737

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Milind Shah ,  Periannan Chidambaram ,  Abdolreza Langari

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L24/29 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/27 ,  H01L2924/01014 ,  H01L2924/1205 ,  H01L2924/14

Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.