公开(公告)号：US11832450B2

公开(公告)日：2023-11-28

申请号：US17867998

申请日：2022-07-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

IPC: G11C11/22 ,  H10B51/30 ,  H01L27/12

CPC classification number: H10B51/30 ,  G11C11/223 ,  H01L27/1211

Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

公开(公告)号：US11830550B2

公开(公告)日：2023-11-28

申请号：US17392830

申请日：2021-08-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Han-Jong Chia ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: G11C14/00 ,  G11C11/22 ,  G11C11/419 ,  H10B10/00 ,  H10B51/30 ,  H10B53/30

CPC classification number: G11C14/0072 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/419 ,  H10B10/12 ,  H10B51/30 ,  H10B53/30

Abstract: Memories are provided. A memory includes a plurality of ferroelectric random access memory (FRAM) cells arranged in a first memory array, and a plurality of static random access memory (SRAM) cells arranged in a second memory array. The first memory array and the second memory array share the same bus. Each of the FRAM cells includes a ferroelectric field-effect transistor (FeFET). A gate structure of the FeFET includes a gate electrode over a channel of the FeFET, and a ferroelectric layer over the gate electrode.

公开(公告)号：US11770934B2

公开(公告)日：2023-09-26

申请号：US17400087

申请日：2021-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Shih-Lien Linus Lu ,  Chia-En Huang ,  Yih Wang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H10B51/20 ,  G11C5/06 ,  H01L23/522

CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223 ,  H01L23/5221

Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

公开(公告)号：US11744060B2

公开(公告)日：2023-08-29

申请号：US17401251

申请日：2021-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Huai-Ying Huang ,  Yu-Ming Lin

IPC: H10B10/00 ,  H01L29/786 ,  H01L27/092

CPC classification number: H10B10/12 ,  H01L27/0922 ,  H01L29/78675 ,  H10B10/18

Abstract: A memory device is provided. The memory device includes a plurality of memory cells. Each memory cell includes a latch circuit formed of N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The NFETs are formed at a surface of a semiconductor substrate, and the PFETs are disposed at an elevated level over the NFETs.

公开(公告)号：US20230268438A1

公开(公告)日：2023-08-24

申请号：US18308791

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H10B51/20

CPC classification number: H01L29/78391 ,  H01L29/78693 ,  H01L29/78642 ,  H01L29/4908 ,  H10B51/20

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

公开(公告)号：US11676867B2

公开(公告)日：2023-06-13

申请号：US17397638

申请日：2021-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Ching-Hua Lee ,  Clement Hsingjen Wann ,  Yu-Ming Lin

IPC: H01L21/8238 ,  H01L21/268 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L29/40 ,  H01L21/02 ,  H01L29/45

CPC classification number: H01L21/823814 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/823821 ,  H01L29/401 ,  H01L29/45 ,  H01L29/665

Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first conductive region and a second conductive region. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region.

公开(公告)号：US20230123292A1

公开(公告)日：2023-04-20

申请号：US18080677

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sai-Hooi Yeong ,  Kai-Hsuan Lee ,  Yu-Ming Lin ,  Chi-On Chui

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L27/088 ,  H01L21/764

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

公开(公告)号：US11568912B2

公开(公告)日：2023-01-31

申请号：US17196131

申请日：2021-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chao-I Wu ,  Chih-Yu Chang ,  Yu-Ming Lin

IPC: G11C11/22 ,  H01L27/1159

Abstract: A memory cell includes a write bit line, a write transistor and a read transistor. The write transistor is coupled between the write bit line and a first node. The read transistor is coupled to the write transistor by the first node. The read transistor includes a ferroelectric layer. The write transistor is configured to set a stored data value of the memory cell by a write bit line signal that adjusts a polarization state of the read transistor. The polarization state corresponds to the stored data value.

公开(公告)号：US11522046B2

公开(公告)日：2022-12-06

申请号：US17401728

申请日：2021-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chih-Yu Chang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/11587 ,  H01L27/088 ,  H01L29/78 ,  G11C11/22

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The method for forming a semiconductor structure includes forming a semiconductor stack over a substrate, wherein the semiconductor stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatively stacked, patterning the semiconductor stack to form a first fin and a second fin adjacent to the first fin, and removing the second semiconductor layers to obtain a first group of nanosheets over the first fin and a second group of nanosheets over the second fin, wherein a lateral spacing between one of the nanosheets in the first group and a corresponding nanosheet in the second group is smaller than a vertical spacing between each of the nanosheets in the first group.

公开(公告)号：US20220384459A1

公开(公告)日：2022-12-01

申请号：US17880803

申请日：2022-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Lu ,  Han-Jong Chia ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/66 ,  H01L29/786

Abstract: Provided is a ferroelectric memory device having a multi-layer stack disposed over a substrate and including a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A plurality of ferroelectric portions are discretely disposed between the channel layer and the plurality of conductive layers. The plurality of ferroelectric portions are vertically separated from one another by one or more non-zero distances.