公开(公告)号：US20160181404A1

公开(公告)日：2016-06-23

申请号：US14574497

申请日：2014-12-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yao Wen ,  Sai-Hooi Yeong ,  Sheng-Chen Wang

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0207 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/78615

Abstract: A FinFET having fin back biasing and methods of forming the same are disclosed. The FinFET includes a substrate and a fin over the substrate. The fin includes a source region, a drain region, a channel region, and a biasing region. The source and drain regions sandwich the channel region. The channel region and the biasing region sandwich one of the source and drain regions. The FinFET further includes a gate over the substrate. The gate engages the fin adjacent to the channel region, thereby forming a field effect transistor (FET). The biasing region is configured to bias the FET body effect when a voltage is applied to the biasing region. From a cross sectional view, the source region and the biasing region each have a substantially rectangular profile, wherein the source region is taller and wider than the biasing region.

Abstract translation: 公开了具有翅片后偏置的FinFET及其形成方法。 FinFET包括衬底和衬底上的翅片。 鳍包括源极区，漏极区，沟道区和偏置区。 源区和漏区夹着沟道区。 沟道区域和偏置区域夹着源区和漏区之一。 FinFET还包括在衬底上的栅极。 栅极接近与沟道区相邻的鳍，从而形成场效应晶体管（FET）。 偏置区域被配置为当将电压施加到偏置区域时偏置FET体效应。 源区域和偏置区域从横截面视图中分别具有基本上矩形的轮廓，其中源区域比偏置区域更高和更宽。

公开(公告)号：US20160155826A1

公开(公告)日：2016-06-02

申请号：US15018709

申请日：2016-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Clement Hsingjen Wann ,  Ling-Yen Yeh ,  Chi-Yuan Shih ,  Yi-Tang Lin ,  Chih-Sheng Chang

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66818 ,  H01L21/2236 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211

Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.

公开(公告)号：US09312365B2

公开(公告)日：2016-04-12

申请号：US14487103

申请日：2014-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09306069B2

公开(公告)日：2016-04-05

申请号：US14024148

申请日：2013-09-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen ,  Chao Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/66818 ,  H01L21/2253 ,  H01L21/30604 ,  H01L21/31155 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.

Abstract translation: 本发明涉及鳍状场效应晶体管（FinFET）。 示例性FinFET包括包含主表面的衬底; 从主表面突出的翅片结构，包括下部，包括具有第一晶格常数的第一半导体材料; 包括第一半导体材料的上部，其中上部的底部包括具有第一峰值浓度的掺杂剂; 下部和上部之间的中间部分，其中中间部分包括具有不同于第一晶格常数的第二晶格常数的第二半导体材料; 以及围绕所述翅片结构的隔离结构，其中所述隔离结构的与所述上部的底部相邻的部分包括具有等于或大于所述第一峰值浓度的第二峰值浓度的所述掺杂剂。

公开(公告)号：US20160087041A1

公开(公告)日：2016-03-24

申请号：US14959821

申请日：2015-12-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC: H01L29/165 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.

Abstract translation: 本公开描述了鳍式场效应晶体管（FinFET）。 该器件包括在衬底上的一个或多个翅片结构，每个具有源极/漏极（S / D）特征和高k /金属栅极（HK / MG）。 第一栅极区域中的第一HK / MG包裹在第一鳍结构的上部，第一鳍结构包括作为其上部的外延硅（Si）层和外延生长硅锗（SiGe），其中硅 其外层为锗氧化物（SiGeO），其中间部分为基底，底部为底部。 在第二栅极区域中的第二HK / MG包裹在第二鳍结构的上部，第二鳍结构包括作为其上部的外延SiGe层，作为其上部中间部分的外延Si层，外延SiGe层 作为其下部中间部分，基板作为其底部。

公开(公告)号：US20160079428A1

公开(公告)日：2016-03-17

申请号：US14839915

申请日：2015-08-28

Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION

Inventor： MENG ZHAO

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7853 ,  H01L21/26533 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7848

Abstract: A method for forming a FinFET transistor structure includes providing a substrate with a buried oxide layer and a layer of first semiconductor material. One or more fin structures are formed on the first layer of semiconductor material using a hard mask layer. Sidewall spacers are formed on sidewalls of the fin structures and the hard mask layer. An angled oxygen ion implantation is carried out using the hard mask and side walls as the mask. Next, an annealing process is performed to form oxide diffusion regions. Then, the oxide diffusion regions are removed, and the exposed first semiconductor material layer is etched to expose portions of the buried oxide layer. The resulting fin structure has recessed regions formed on the sidewalls, and the fin structure has a bottom portion below the recessed regions that is wider than a top portion.

Abstract translation: 一种用于形成FinFET晶体管结构的方法包括：提供具有掩埋氧化物层和第一半导体材料层的衬底。 使用硬掩模层在第一半导体材料层上形成一个或多个翅片结构。 侧壁间隔件形成在翅片结构和硬掩模层的侧壁上。 使用硬掩模和侧壁作为掩模进行成角度的氧离子注入。 接下来，进行退火处理以形成氧化物扩散区域。 然后，去除氧化物扩散区，并且暴露的第一半导体材料层被蚀刻以暴露出掩埋氧化物层的部分。 所得到的翅片结构具有形成在侧壁上的凹陷区域，翅片结构具有比顶部宽的凹陷区域下方的底部。

公开(公告)号：US20150357187A1

公开(公告)日：2015-12-10

申请号：US14725656

申请日：2015-05-29

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tamotsu MORIMOTO ,  Yusuke MURAKI ,  Kazuaki NISHIMURA

IPC: H01L21/02

CPC classification number: H01L21/02334 ,  H01L21/02057 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02337 ,  H01L21/3065 ,  H01L21/76892 ,  H01L29/66818

Abstract: A modification processing method includes preparing a substrate having a silicon layer on which a damage layer is formed through plasma processing. The method further includes removing the damage layer formed on the silicon layer by processing the substrate with a first process gas containing a fluorine gas.

Abstract translation: 修改处理方法包括制备具有通过等离子体处理形成有损伤层的硅层的基板。 该方法还包括通过用含氟气体的第一工艺气体处理衬底来去除形成在硅层上的损伤层。

公开(公告)号：US09190518B2

公开(公告)日：2015-11-17

申请号：US14273373

申请日：2014-05-08

Applicant: Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

Inventor： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423

CPC classification number: H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US09184232B2

公开(公告)日：2015-11-10

申请号：US14538046

申请日：2014-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/06 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US20150303198A1

公开(公告)日：2015-10-22

申请号：US14254072

申请日：2014-04-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ka-Hing Fung ,  Chih-Sheng Chang ,  Zhiqiang Wu

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/161 ,  H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L29/16 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7853

Abstract: The present disclosure provides a method for fabricating a fin-like field-effect transistor (FinFET). The method includes forming a first fin structures over a substrate, forming a patterned oxidation-hard-mask (OHM) over the substrate to expose the first fin structure in a first gate region of a n-type FET region, forming a semiconductor oxide feature in a middle portion of the first fin structure in the first gate region, forming a second fin structure in a PFET region, forming dummy gates, forming source/drain (S/D) features, replacing the dummy gates by a first high-k/metal gate (HK/MG) in the NFET region and a second HK/MG in the PFET region.

Abstract translation: 本公开提供了一种制造鳍状场效应晶体管（FinFET）的方法。 该方法包括在衬底上形成第一鳍片结构，在衬底上形成图案化氧化 - 硬掩模（OHM），以暴露n型FET区域的第一栅极区域中的第一鳍结构，形成半导体氧化物特征 在第一栅极区域中的第一鳍结构的中间部分中，在PFET区域中形成第二鳍结构，形成虚拟栅极，形成源极/漏极（S / D）特征，用第一高k /金属栅极（HK / MG）和PFET区域中的第二HK / MG。