公开(公告)号：US09190518B2

公开(公告)日：2015-11-17

申请号：US14273373

申请日：2014-05-08

申请人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US20080135894A1

公开(公告)日：2008-06-12

申请号：US12009122

申请日：2008-01-15

申请人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

发明人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC分类号： H01L29/94

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US5874358A

公开(公告)日：1999-02-23

申请号：US805961

申请日：1997-02-25

申请人： Alan M. Myers ,  Peter K. Charvat ,  Thomas A. Letson ,  Shi-ning Yang ,  Peng Bai

发明人： Alan M. Myers ,  Peter K. Charvat ,  Thomas A. Letson ,  Shi-ning Yang ,  Peng Bai

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/302

CPC分类号： H01L21/76805 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76804 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/915

摘要： A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

公开(公告)号：US08502351B2

公开(公告)日：2013-08-06

申请号：US13243441

申请日：2011-09-23

申请人： Uday Shah ,  Brian Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/06

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

公开(公告)号：US07821044B2

公开(公告)日：2010-10-26

申请号：US12009122

申请日：2008-01-15

申请人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

发明人： Mark T. Bohr ,  Steven J. Keating ,  Thomas A. Letson ,  Anand S. Murthy ,  Donald W. O'Neill ,  Willy Rachmady

IPC分类号： H01L21/336 ,  H01L29/06

CPC分类号： H01L29/045 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

摘要翻译： 实施例是改进的晶体管结构和制造该结构的方法。 特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能 并且在源极和漏极与硅化物之间的界面处降低接触电阻。

公开(公告)号：US5619071A

公开(公告)日：1997-04-08

申请号：US515318

申请日：1995-08-15

申请人： Alan M. Myers ,  Peter K. Charvat ,  Thomas A. Letson ,  Shi-ning Yang ,  Peng Bai

发明人： Alan M. Myers ,  Peter K. Charvat ,  Thomas A. Letson ,  Shi-ning Yang ,  Peng Bai

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/41

CPC分类号： H01L21/76805 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76804 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/915

摘要： A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

摘要翻译： 一种新颖的高性能和可靠的互连结构，用于防止通过分层。 本发明的互连结构包括通孔连接，其延伸到下面的互连线并将其下切以将通孔连接锁定到互连线中。

公开(公告)号：US5470790A

公开(公告)日：1995-11-28

申请号：US324763

申请日：1994-10-17

申请人： Alan M. Myers ,  Peter K. Charvat ,  Thomas A. Letson ,  Shi-ning Yang ,  Peng Bai

发明人： Alan M. Myers ,  Peter K. Charvat ,  Thomas A. Letson ,  Shi-ning Yang ,  Peng Bai

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/302

CPC分类号： H01L21/76805 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76804 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/915

摘要： A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

摘要翻译： 一种新颖的高性能和可靠的互连结构，用于防止通过分层。 本发明的互连结构包括通孔连接，其延伸到下面的互连线并将其下切以将通孔连接锁定到互连线中。

公开(公告)号：US20140239358A1

公开(公告)日：2014-08-28

申请号：US14273373

申请日：2014-05-08

申请人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

公开(公告)号：US08749026B2

公开(公告)日：2014-06-10

申请号：US13908858

申请日：2013-06-03

申请人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/06

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。

公开(公告)号：US20120012934A1

公开(公告)日：2012-01-19

申请号：US13243441

申请日：2011-09-23

申请人： Uday Shah ,  Brian Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

发明人： Uday Shah ,  Brian Doyle ,  Justin K. Brask ,  Robert S. Chau ,  Thomas A. Letson

IPC分类号： H01L29/78

CPC分类号： H01L29/42384 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L29/7856 ,  H01L2924/13067 ,  Y10S438/978

摘要： A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

摘要翻译： 具有形成在基板的绝缘层上的半导体本体的非平面半导体器件。 半导体本体具有与形成在绝缘层上的底表面相对的顶表面和一对横向相对的侧壁，其中在顶表面处的横向相对侧壁之间的距离大于底表面处的距离。 栅电介质层形成在半导体本体的顶表面和半导体本体的侧壁上。 栅极电极形成在半导体本体的顶表面和侧壁上的栅介质层上。 在栅电极的相对侧的半导体本体中形成一对源极/漏极区域。