公开(公告)号：US11810882B2

公开(公告)日：2023-11-07

申请号：US17684292

申请日：2022-03-01

申请人： Micron Technology, Inc.

发明人： Wei Zhou

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0518 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05173 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05183 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/11826 ,  H01L2224/11827 ,  H01L2224/11845 ,  H01L2224/11849 ,  H01L2224/13009 ,  H01L2224/1318 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/8185 ,  H01L2224/81815 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/07025

摘要： A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

公开(公告)号：US20230352460A1

公开(公告)日：2023-11-02

申请号：US18091072

申请日：2022-12-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Eunsu LEE ,  Jangwoo LEE ,  Doyoung JANG

IPC分类号： H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC分类号： H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2224/81385 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13124 ,  H01L2224/13113 ,  H01L2224/81447

摘要： A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.

公开(公告)号：US20230352449A1

公开(公告)日：2023-11-02

申请号：US18132571

申请日：2023-04-10

申请人： SJ Semiconductor(Jiangyin) Corporation

发明人： Yenheng Chen ,  Chengchung Lin

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H10B80/00 ,  H01L23/29

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L21/56 ,  H01L24/11 ,  H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H10B80/00 ,  H01L23/296 ,  H01L2225/0651 ,  H01L2224/05144 ,  H01L2224/05139 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13111

摘要： A fan-out stacked semiconductor package structure and a packaging method thereof are disclosed. The structure includes a three-dimensional memory chip package unit and a two-dimensional fan-out peripheral circuit chip SiP package unit. The three-dimensional memory chip package unit includes: at least two memory chips laminated in a stepped configuration; a first rewiring layer; wire bonding structures, each of which being electrically connected to the bonding pad and the first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The two-dimensional fan-out peripheral circuit chip SiP package unit includes: a second rewiring layer; at least one peripheral circuit chip; a third rewiring layer, bonded to the peripheral circuit chip; metal connection pillars; a second encapsulating layer, encapsulating the peripheral circuit chip and the metal connection pillars; and second metal bumps, formed on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer.

公开(公告)号：US20230352317A1

公开(公告)日：2023-11-02

申请号：US17897268

申请日：2022-08-29

申请人： LING-YI CHUANG

发明人： LING-YI CHUANG

IPC分类号： H01L23/29 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3135 ,  H01L24/08 ,  H01L24/13 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2224/13147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/95001 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1811 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/37001

摘要： A method for manufacturing a semiconductor device and a semiconductor device are provided. The method includes: providing a carrier; providing multiple wafers each including multiple chips; stacking the multiple wafers on the carrier sequentially in a vertical direction, and bonding the chips respectively disposed on two adjacent ones of the wafers in a one-to-one correspondence; performing a first cutting process on the multiple wafers to form multiple cutting slots located above the carrier and penetrating through the multiple wafers to divide the multiple wafers into multiple chip stacks each including multiple chips stacked in the vertical direction, and the carrier enabling the chip stacks to be in an un-separated state; forming a cladding layer covering at least one chip stack; and performing a second cutting process on the cladding layer along the cutting slots to form multiple chip stacks covered with the cladding layer.

公开(公告)号：US20230317532A1

公开(公告)日：2023-10-05

申请号：US17987132

申请日：2022-11-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Il Geun JUNG ,  Sung Jin KIM ,  Sang-Ki KIM ,  Joong Won SHIN ,  Sung Yun WOO ,  Sang Hyeon JEON ,  Ji Min CHOI

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L22/32 ,  H01L24/06 ,  H01L25/0657 ,  H01L2224/06515 ,  H01L2224/0401 ,  H01L2224/02373 ,  H01L2224/13155 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13144 ,  H01L24/13 ,  H01L2224/13111

摘要： A semiconductor device includes a substrate with first and second surfaces, a first test pad on the first surface of the substrate, a first bump pad on the first surface of the substrate and spaced apart from the first test pad in a first direction, a second bump pad on the first surface of the substrate and spaced apart from the first bump pad, a second test pad on the first surface of the substrate and spaced apart from the second bump pad in the first direction, a first wiring layer in the first direction and electrically connecting the first test pad to the first bump pad, a second wiring layer in the first direction, spaced apart from the first wiring layer, and electrically connecting the second test pad to the second bump pad, and a first bump connected to each of the first and second bump pads.

公开(公告)号：US20230298937A1

公开(公告)日：2023-09-21

申请号：US17962687

申请日：2022-10-10

申请人： SK hynix Inc.

发明人： Jin Woong KIM ,  Ju Heon YANG

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L21/7684 ,  H01L2224/13147 ,  H01L24/13

摘要： There is provided a semiconductor device including through vias and a method of manufacturing the same. The semiconductor device includes a substrate including a first via hole and a second via hole, a first through via formed in the first via hole, a second through via formed in the second via hole, an insulating layer first portion formed between a sidewall surface of the first via hole and the first through via, and an insulating layer second portion formed between a sidewall surface of the second via hole and the second through via. The insulating layer second portion is thinner than the insulating layer first portion, and the second through via is wider than the first through via,

公开(公告)号：US11762146B2

公开(公告)日：2023-09-19

申请号：US17719808

申请日：2022-04-13

申请人： Analog Photonics LLC

发明人： Michael Robert Watts ,  Benjamin Roy Moss ,  Ehsan Shah Hosseini ,  Christopher Vincent Poulton ,  Peter Nicholas Russo

IPC分类号： G02B6/13 ,  G02B6/12 ,  G02B6/42 ,  G02B7/00 ,  G02B27/00 ,  G02F1/01 ,  H01S5/024 ,  H01S5/02375 ,  H01L21/56 ,  H01L23/00 ,  H01L31/105 ,  H01L31/18 ,  H01L23/31 ,  H01S5/02326 ,  H01S5/02345

CPC分类号： G02B6/13 ,  G02B6/12 ,  G02B6/428 ,  G02B6/4239 ,  G02B6/4245 ,  G02B7/008 ,  G02B27/0068 ,  G02B27/0087 ,  G02F1/011 ,  H01S5/02375 ,  H01S5/02469 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L31/105 ,  H01L31/1804 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01S5/02326 ,  H01S5/02345 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099

摘要： A plurality of waveguide structures are formed in at least one silicon layer of a first member. The first member includes: a first surface of a first silicon dioxide layer that is attached to a second member that consists essentially of an optically transmissive material having a thermal conductivity less than about 50 W/(m·K), and a second surface of material that was deposited over at least some of the plurality of waveguide structures. An array of phase shifters is formed in one or more layers of the first member. An array of temperature controlling elements are in proximity to the array of phase shifters.

公开(公告)号：US11756912B2

公开(公告)日：2023-09-12

申请号：US17350001

申请日：2021-06-17

申请人： LAPIS Semiconductor Co., Ltd.

发明人： Taiichi Ogumi

IPC分类号： H01L23/00 ,  H01L29/16

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L29/1608 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/11013 ,  H01L2224/13147

摘要： A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

公开(公告)号：US11756911B2

公开(公告)日：2023-09-12

申请号：US16438578

申请日：2019-06-12

申请人： International Business Machines Corporation

发明人： Krishna Tunga ,  Ekta Misra

IPC分类号： H01L23/00

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/0557 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/13014 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13186 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/05144 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13166 ,  H01L2924/00014 ,  H01L2224/05686 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13186 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13124 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/056 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/056 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01013 ,  H01L2924/00014

摘要： The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

公开(公告)号：US20230282604A1

公开(公告)日：2023-09-07

申请号：US18106499

申请日：2023-02-07

申请人： MEDIATEK INC.

发明人： Ta-Jen Yu ,  Tai-Yu Chen ,  Shih-Chin Lin ,  Isabella Song ,  Wen-Chin Tsai

IPC分类号： H01L23/00 ,  H01L25/16 ,  H10B80/00 ,  H01L23/498 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L24/13 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L25/162 ,  H01L25/165 ,  H10B80/00 ,  H01L24/16 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/3135 ,  H01L23/291 ,  H01L23/293 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/05624 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/14361 ,  H01L2924/1431 ,  H01L2224/13644 ,  H01L2224/13082 ,  H01L2224/13575 ,  H01L2224/13005 ,  H01L2224/1357 ,  H01L2924/1011

摘要： A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate in a flip-chip fashion. The logic die has a thickness of 125-350 micrometers. The logic die comprises an active front side, a passive rear side, and an input/output pad provided on the active front side. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and seals the logic die and the plurality of copper cored solder balls in the gap.