公开(公告)号：US20250046724A1

公开(公告)日：2025-02-06

申请号：US18675274

申请日：2024-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H10B80/00

Abstract: Provided is a semiconductor package, the semiconductor package including: a package substrate including an upper surface having a first region and a second region, the second region disposed on a level lower than that of the first region, and a plurality of wiring layers; a first semiconductor chip disposed on the first region of the upper surface of the package substrate and electrically connected to the plurality of wiring layers of the package substrate; a second semiconductor chip disposed on the second region of the upper surface of the package substrate; and an interposer substrate disposed between the second region of the upper surface of the package substrate and the second semiconductor chip and electrically connecting the plurality of wiring layers of the package substrate and the second semiconductor chip.

公开(公告)号：US20250006567A1

公开(公告)日：2025-01-02

申请号：US18394750

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu LEE

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: A semiconductor package includes a substrate including a first surface and a second surface facing each other, a semiconductor chip on the substrate, a passive element disposed spaced apart from the semiconductor chip in a first direction parallel to the first surface of the substrate, and a first insulating pattern on an edge region of the first surface. The substrate includes a recessed portion formed on the first surface, the passive element vertically overlaps the recess portion, and the first insulating pattern protrudes in a second direction perpendicular to the first surface of the substrate.

公开(公告)号：US20230352460A1

公开(公告)日：2023-11-02

申请号：US18091072

申请日：2022-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunsu LEE ,  Jangwoo LEE ,  Doyoung JANG

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2224/81385 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13155 ,  H01L2224/13144 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13124 ,  H01L2224/13113 ,  H01L2224/81447

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.

公开(公告)号：US20220359439A1

公开(公告)日：2022-11-10

申请号：US17564689

申请日：2021-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunsu LEE ,  Dongho KIM ,  Jiyong PARK ,  Jeonghyun LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first bonding pad on a first surface of a first substrate, a first through electrode penetrating through the first substrate and electrically connected to the first bonding pad, a first recess with a desired depth in the first substrate from a second surface of the first substrate and exposing an end portion of the first through electrode, and a second bonding pad in the first recess and electrically connected to the first through electrode, a second semiconductor chip stacked on the second surface of the first substrate and including a third bonding pad on a third surface of a second substrate, and a conductive connection member between the second bonding pad and the third bonding pad. At least a portion of the conductive connection member may be in the first recess.

公开(公告)号：US20240379481A1

公开(公告)日：2024-11-14

申请号：US18619512

申请日：2024-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunsu LEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes: a package substrate having an upper surface and a receiving groove that has a predetermined depth from the upper surface; a first semiconductor chip disposed in the receiving groove; a second semiconductor chip attached to the first semiconductor chip, wherein the second semiconductor chip does not overlap a portion of the first semiconductor chip; an underfill member filling the receiving groove of the package substrate, wherein the underfill member includes a first cover portion and a second cover portion, wherein the first cover portion fills a gap between the first semiconductor chip and a bottom surface of the receiving groove, and the second cover portion covers the portion of the first semiconductor chip that is not overlapped by the second semiconductor chip; and a molding member covering the first semiconductor chip, the second semiconductor chip and the underfill member and disposed on the package substrate.

公开(公告)号：US20230114274A1

公开(公告)日：2023-04-13

申请号：US17841155

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyun LEE ,  Hwanpil PARK ,  Jongbo SHIM ,  Eunsu LEE ,  Jangwoo LEE

IPC: H01L23/31 ,  H01L23/498 ,  H01L49/02

Abstract: A semiconductor package includes a redistribution structure having a first surface, an opposite second surface, and a redistribution layer between the first surface and the second surface. A semiconductor chip is on the first surface of the redistribution structure and is electrically connected to the redistribution layer. An encapsulant is on at least a portion of the semiconductor chip. A passive element is on the second surface of the redistribution structure. The passive element includes a connection surface facing the second surface, a connection terminal on the connection surface, a non-connection surface opposite to the connection surface, and a side surface extending from the connection surface to the non-connection surface. A connection bump is adjacent the passive element on the second surface and is electrically connected to the redistribution layer. A sealing material is on at least a portion of the connection surface, the non-connection surface, and the side surface of the passive element.