公开(公告)号：US20160232969A1

公开(公告)日：2016-08-11

申请号：US14619985

申请日：2015-02-11

Applicant: SANDISK 3D LLC

Inventor： Gopinath Balakrishnan ,  Yibo Yin ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/12 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0088

Abstract: Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

Abstract translation: 独立读出放大器寻址在一个列地址周期内为单个托架内的各个读出放大器组提供单独的列地址。 存储器系统确定是否可以跳过单个存储单元或一个隔行列中的位。 对于具有需要编程的至少一个存储单元（或位）的每个读出放大器组，系统确定第一列地址是否可以跳过存储器单元。 如果可以跳过来自读出放大器组的第一列地址的位或存储单元，则系统从需要编程的组确定具有列地址的下一位。 系统在第一列地址周期中对下一列地址进行分组编程。 在单列地址周期期间，系统可以为托架内的不同读出放大器组编程不同的列地址。

公开(公告)号：US09318194B1

公开(公告)日：2016-04-19

申请号：US14500476

申请日：2014-09-29

Applicant: SanDisk 3D LLC

Inventor： Chang Siau ,  Jeffrey Koon Yee Lee ,  Tianhong Yan ,  Yingchang Chen ,  Gopinath Balakrishnan ,  Tz-yi Liu

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C16/28 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0054

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

Abstract translation: 提供一种用于读取非易失性存储器系统的存储单元的方法。 该方法包括在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内为存储器单元生成硬比特和N个软比特。

公开(公告)号：US20140185351A1

公开(公告)日：2014-07-03

申请号：US14201899

申请日：2014-03-09

Applicant: SANDISK 3D LLC

Inventor： Tianhong Yan ,  Tz-yi Liu ,  Roy E. Scheuerlein

IPC: G11C13/00 ,  G11C5/02

CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/71 ,  G11C2213/73 ,  G11C2213/77

Abstract: A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.

Abstract translation: 公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块 存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线， 全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路 与一个或多个选择电路和全局数据线的通信。 控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

公开(公告)号：US20160139828A1

公开(公告)日：2016-05-19

申请号：US14547473

申请日：2014-11-19

Applicant: SANDISK 3D LLC

Inventor： Tianhong Yan ,  Tz-yi Liu

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  Y02D10/154

Abstract: Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.

Abstract translation: 描述了包括多个存储器阵列的非易失性存储器的方法，其中多个存储器阵列的每个存储器阵列可以独立地执行SET操作，RESET操作或读取操作。 独立地设置或重置存储器阵列的能力允许在第一存储器阵列内的第一组存储器单元上执行SET操作，同时对第二存储器阵列中的第二组存储器单元执行复位操作 。 在一些情况下，第一存储器阵列可以与第一存储器托架相关联，并且第二存储器阵列可以与第二存储器托架相关联。 每个存储器托架可以包括存储器阵列，读/写电路和用于基于存储器单元分组来确定存储器单元分组和编程存储器阵列内的存储器单元的控制电路。

公开(公告)号：US20160020389A1

公开(公告)日：2016-01-21

申请号：US14716382

申请日：2015-05-19

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: H01L45/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US09202566B2

公开(公告)日：2015-12-01

申请号：US14246052

申请日：2014-04-05

Applicant: SanDisk 3D LLC

Inventor： Chang Siau ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/77

Abstract: Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.

Abstract translation: 描述了在非易失性存储系统中形成非易失性存储元件的方法。 在一些实施例中，可以执行多个形成操作，其中在形成其他非易失性存储元件之前形成位于与字线梳相关联的多个字线手指的远端附近的非易失性存储元件。 在一个示例中，非易失性存储元件可以并行地形成在多个字线手指中的每一个中，并且以在多个字线手指中的远端附近形成非易失性存储元件的顺序 在形成其他非易失性存储元件之前的多个字线指。 在成形操作期间形成的每个非易失性存储元件可以是电流限制的，同时在非易失性存储元件上施加形成电压。

公开(公告)号：US08780605B2

公开(公告)日：2014-07-15

申请号：US13735983

申请日：2013-01-07

Applicant: SanDisk 3D LLC

Inventor： Tianhong Yan ,  George Samachisa

IPC: G11C11/00 ,  G11C11/06

CPC classification number: G11C13/0007 ,  B82Y10/00 ,  G11C11/06035 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/025 ,  G11C16/10 ,  G11C2013/0045 ,  G11C2013/0088 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/55 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/78 ,  H01L23/528 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.

Abstract translation: 特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。 单面字线架构为每行存储器元件专门提供字线，而不是在两行存储器元件之间共享一个字线，从而避免跨越字线跨越阵列链接存储元件。 虽然存储器元件行也被对应的局部位线行访问，但是在局部位线的相邻行之间没有扩展耦合，因此没有扩展超出字线的漏电流。

公开(公告)号：US20140022848A1

公开(公告)日：2014-01-23

申请号：US13973218

申请日：2013-08-22

Applicant: SANDISK 3D LLC

Inventor： George Samachisa ,  Luca Fasoli ,  Yan Li ,  Tianhong Yan

IPC: G11C16/06

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0097 ,  G11C16/06 ,  G11C2013/0054 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/149 ,  H01L45/1675

Abstract: A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

Abstract translation: 三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。 存储元件跨越位于半导体衬底上方不同距离的多个平面形成。 所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。 在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。 提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。 当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

公开(公告)号：US09715925B2

公开(公告)日：2017-07-25

申请号：US14502093

申请日：2014-09-30

Applicant: SanDisk 3D LLC

Inventor： Chang Siau ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0021 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2207/2254 ,  G11C2213/71

Abstract: Methods for operating a non-volatile storage system are described. The non-volatile storage system includes a plurality of bit lines, a plurality of word line combs each comprising a plurality of word lines, and a plurality of resistance-switching memory elements. Each resistance-switching memory element is coupled between one of the bit lines and one of the word lines. The method includes calibrating a plurality of bias voltages for the word lines and bit lines based on estimates of data values stored in the resistance-switching memory elements.

公开(公告)号：US09455301B2

公开(公告)日：2016-09-27

申请号：US14715579

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: H01L27/24 ,  G11C13/00 ,  G06F11/10 ,  H01L29/786 ,  H01L45/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 在存储器操作期间通过存储器阵列的未选择存储单元减少漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。