公开(公告)号：US09390793B1

公开(公告)日：2016-07-12

申请号：US14663786

申请日：2015-03-20

Applicant: SanDisk 3D LLC

Inventor： Anurag Nigam ,  Yingchang Chen

IPC: G11C7/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C13/0026 ,  G11C2013/0054

Abstract: A non-volatile memory includes a sense amplifier that uses a reference bit line. The sense amplifier includes a first capacitor coupled to a selected bit line and a second capacitor coupled to a reference bit line. The reference capacitor compensates for displacement currents in the selected bit line during sensing. Both plates of the capacitors are utilized to cancel leakage currents. The top plates of the capacitors are precharged then discharged during a sense phase. The selected bit line capacitor is discharged based on the selected cell current and the leakage current. The amount of discharge is transferred to the bottom plate of each capacitor, followed by discharging the bottom plates. The capacitor for the selected bit line is discharged based on the leakage current. In this manner, the correction phase facilitates a compensation based on the leakage current so that the selected cell current can be determined.

Abstract translation: 非易失性存储器包括使用参考位线的读出放大器。 感测放大器包括耦合到所选位线的第一电容器和耦合到参考位线的第二电容器。 参考电容器在感测期间补偿所选位线中的位移电流。 电容器的两个板都用于消除泄漏电流。 电容器的顶板预充电然后在感应阶段放电。 所选位线电容器根据选定的电池电流和漏电流放电。 放电量转移到每个电容器的底板，然后放电底板。 所选位线的电容器根据漏电流放电。 以这种方式，校正阶段有助于基于漏电流的补偿，使得可以确定所选择的单元电流。

公开(公告)号：US20140347912A1

公开(公告)日：2014-11-27

申请号：US14283034

申请日：2014-05-20

Applicant: SANDISK 3D LLC

Inventor： Chang Siau ,  Xiaowei Jiang ,  Yingchang Chen

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/0069 ,  G11C16/24 ,  G11C16/26 ,  G11C2013/0042 ,  G11C2013/0045 ,  G11C2207/063

Abstract: Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.

Abstract translation: 描述了使用闭环反馈对位线进行预充电的方法。 在一个实施例中，读出放大器可以包括位线预充电电路，用于在感测连接到位线的存储器单元之前将位线设置为读取电压。 位线预充电电路可以包括具有第一栅极的源极跟随器配置的第一晶体管和电耦合到位线的第一源节点。 通过将来自第一源节点的本地反馈应用于第一门，可以减少位线建立时间。 在一些情况下，施加到第一栅极的第一电压可以基于从第一位线汲取的第一电流来确定。 因此，施加到第一栅极的第一电压可以随时间而变化，这取决于连接到位线的所选择的存储器单元的电导率。

公开(公告)号：US08885400B2

公开(公告)日：2014-11-11

申请号：US13773078

申请日：2013-02-21

Applicant: SanDisk 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C13/00 ,  G11C7/00 ,  G11C11/56

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

公开(公告)号：US20140233329A1

公开(公告)日：2014-08-21

申请号：US13773078

申请日：2013-02-21

Applicant: SANDISK 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

公开(公告)号：US09361976B2

公开(公告)日：2016-06-07

申请号：US14539150

申请日：2014-11-12

Applicant: SanDisk 3D LLC

Inventor： Chang Siau ,  Yingchang Chen

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/067 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0061 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2213/71

Abstract: Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.

Abstract translation: 提供了与存储器阵列一起使用的方法，所述存储器阵列包括耦合到所选择的字线和选定位线的所选择的存储器单元，所选择的字线被偏置在读取电压。 该方法包括将感测放大器耦合到所选择的位线，读出放大器包括电容器积分器，单晶体管放大器和电平转换器，使用单晶体管放大器将所选位线保持在大致0V的电压，并且 电平移位器，并将所选位线电流积分到电容积分器上。

公开(公告)号：US08988936B2

公开(公告)日：2015-03-24

申请号：US14506607

申请日：2014-10-04

Applicant: SanDisk 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C13/00 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Abstract translation: 描述了在存储器阵列中的存储器单元的读取和/或写入期间执行并行电压和电流补偿的方法。 在一些实施例中，补偿可以包括基于与存储器单元相关联的存储器阵列区域，位线层和存储器单元方向来调整施加到存储器单元的位线电压和/或位线参考电流。 补偿可以包括根据存储器单元特定特性来调整每个存储器单元上的位线电压和/或位线参考电流。 在一些实施例中，用于读取和/或写入存储器单元的读/写电路可以根据存储器单元是否被表征为存储单元来选择要施加到存储器单元的多个位线电压选项中的位线电压 强，弱或典型的记忆体。

公开(公告)号：US20150023113A1

公开(公告)日：2015-01-22

申请号：US14506607

申请日：2014-10-04

Applicant: SANDISK 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Abstract translation: 描述了在存储器阵列中的存储器单元的读取和/或写入期间执行并行电压和电流补偿的方法。 在一些实施例中，补偿可以包括基于与存储器单元相关联的存储器阵列区域，位线层和存储器单元方向来调整施加到存储器单元的位线电压和/或位线参考电流。 补偿可以包括根据存储器单元特定特性来调整每个存储器单元上的位线电压和/或位线参考电流。 在一些实施例中，用于读取和/或写入存储器单元的读/写电路可以根据存储器单元是否被表征为存储单元来选择要施加到存储器单元的多个位线电压选项中的位线电压 强，弱或典型的记忆体。

公开(公告)号：US20160133320A1

公开(公告)日：2016-05-12

申请号：US14539150

申请日：2014-11-12

Applicant: SanDisk 3D LLC

Inventor： Chang Siau ,  Yingchang Chen

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/067 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/0061 ,  G11C27/024 ,  G11C2013/0054 ,  G11C2213/71

Abstract: Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.

Abstract translation: 提供了与存储器阵列一起使用的方法，所述存储器阵列包括耦合到所选择的字线和选定位线的所选择的存储器单元，所选择的字线被偏置在读取电压。 该方法包括将感测放大器耦合到所选择的位线，读出放大器包括电容器积分器，单晶体管放大器和电平转换器，使用单晶体管放大器将所选位线保持在大致0V的电压，并且 电平移位器，并将所选位线电流积分到电容积分器上。

公开(公告)号：US20160093373A1

公开(公告)日：2016-03-31

申请号：US14500476

申请日：2014-09-29

Applicant: SanDisk 3D LLC

Inventor： Chang Siau ,  Jeffrey Koon Yee Lee ,  Tianhong Yan ,  Yingchang Chen ,  Gopinath Balakrishnan ,  Tz-yi Liu

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C16/28 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0054

Abstract: A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

公开(公告)号：US09224466B1

公开(公告)日：2015-12-29

申请号：US14499717

申请日：2014-09-29

Applicant: SanDisk 3D LLC

Inventor： Yingchang Chen ,  Anurag Nigam

IPC: G11C7/02 ,  G11C13/00 ,  G11C7/06

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/065 ,  G11C11/24 ,  G11C13/0023 ,  G11C13/0061 ,  G11C27/024 ,  G11C2213/71 ,  G11C2213/77

Abstract: Methods and apparatus are provided for reading a selected memory cell of a memory array using a sense amplifier that includes a first capacitor and a second capacitor. The selected memory cell is coupled to a bit line and a selected word line. A first noise voltage is generated on the first capacitor, and a selected memory cell voltage and a second noise voltage are generated on the second capacitor. The first noise voltage is an estimate of the second noise voltage. An output signal value is generated proportional to a difference between the selected memory cell voltage and a reference voltage, and a difference between the first noise voltage and second noise voltage. The output signal value is used to determine a data value for the selected memory cell.

Abstract translation: 提供了使用包括第一电容器和第二电容器的读出放大器读取存储器阵列的选定存储单元的方法和装置。 所选择的存储单元耦合到位线和所选择的字线。 在第一电容器上产生第一噪声电压，并且在第二电容器上产生选择的存储单元电压和第二噪声电压。 第一噪声电压是第二噪声电压的估计。 产生与选择的存储单元电压和参考电压之间的差成比例的输出信号值，以及第一噪声电压和第二噪声电压之间的差。 输出信号值用于确定所选存储单元的数据值。