公开(公告)号：US20150023115A1

公开(公告)日：2015-01-22

申请号：US14506610

申请日：2014-10-04

Applicant: SANDISK 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

公开(公告)号：US08934295B1

公开(公告)日：2015-01-13

申请号：US14506610

申请日：2014-10-04

Applicant: Sandisk 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C13/00 ,  G11C7/12 ,  G11C11/56

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

公开(公告)号：US20140233327A1

公开(公告)日：2014-08-21

申请号：US14254883

申请日：2014-04-16

Applicant: SANDISK 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Abstract translation: 描述了在存储器阵列中的存储器单元的读取和/或写入期间执行并行电压和电流补偿的方法。 在一些实施例中，补偿可以包括基于与存储器单元相关联的存储器阵列区域，位线层和存储器单元方向来调整施加到存储器单元的位线电压和/或位线参考电流。 补偿可以包括根据存储器单元特定特性来调整每个存储器单元上的位线电压和/或位线参考电流。 在一些实施例中，用于读取和/或写入存储器单元的读/写电路可以根据存储器单元是否被表征为存储单元来选择要施加到存储器单元的多个位线电压选项中的位线电压 强，弱或典型的记忆体。

公开(公告)号：US20140353573A1

公开(公告)日：2014-12-04

申请号：US14462374

申请日：2014-08-18

Applicant: SANDISK 3D LLC

Inventor： Pankaj Kalra ,  Chandrasekhar Gorla ,  Masaaki Higashitani

IPC: H01L27/24 ,  H01L21/3215 ,  H01L21/3205 ,  H01L49/02 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L28/20 ,  H01L29/78642 ,  H01L31/0547 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y02E10/52

Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

Abstract translation: 描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。 在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。 例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。 嵌入式电阻器可以包括存储器单元内的多晶硅层。 可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

公开(公告)号：US08885400B2

公开(公告)日：2014-11-11

申请号：US13773078

申请日：2013-02-21

Applicant: SanDisk 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C13/00 ,  G11C7/00 ,  G11C11/56

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

公开(公告)号：US20140233329A1

公开(公告)日：2014-08-21

申请号：US13773078

申请日：2013-02-21

Applicant: SANDISK 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

公开(公告)号：US09318533B2

公开(公告)日：2016-04-19

申请号：US14462374

申请日：2014-08-18

Applicant: SANDISK 3D LLC

Inventor： Pankaj Kalra ,  Chandrasekhar Gorla ,  Masaaki Higashitani

IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00 ,  H01L49/02 ,  H01L29/786

CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L28/20 ,  H01L29/78642 ,  H01L31/0547 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y02E10/52

Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

Abstract translation: 描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。 在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。 例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。 嵌入式电阻器可以包括存储器单元内的多晶硅层。 可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

公开(公告)号：US08988936B2

公开(公告)日：2015-03-24

申请号：US14506607

申请日：2014-10-04

Applicant: SanDisk 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C13/00 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Abstract translation: 描述了在存储器阵列中的存储器单元的读取和/或写入期间执行并行电压和电流补偿的方法。 在一些实施例中，补偿可以包括基于与存储器单元相关联的存储器阵列区域，位线层和存储器单元方向来调整施加到存储器单元的位线电压和/或位线参考电流。 补偿可以包括根据存储器单元特定特性来调整每个存储器单元上的位线电压和/或位线参考电流。 在一些实施例中，用于读取和/或写入存储器单元的读/写电路可以根据存储器单元是否被表征为存储单元来选择要施加到存储器单元的多个位线电压选项中的位线电压 强，弱或典型的记忆体。

公开(公告)号：US20150023113A1

公开(公告)日：2015-01-22

申请号：US14506607

申请日：2014-10-04

Applicant: SANDISK 3D LLC

Inventor： Yingchang Chen ,  Pankaj Kalra ,  Chandrasekhar Gorla

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/00 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0076

Abstract: Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

Abstract translation: 描述了在存储器阵列中的存储器单元的读取和/或写入期间执行并行电压和电流补偿的方法。 在一些实施例中，补偿可以包括基于与存储器单元相关联的存储器阵列区域，位线层和存储器单元方向来调整施加到存储器单元的位线电压和/或位线参考电流。 补偿可以包括根据存储器单元特定特性来调整每个存储器单元上的位线电压和/或位线参考电流。 在一些实施例中，用于读取和/或写入存储器单元的读/写电路可以根据存储器单元是否被表征为存储单元来选择要施加到存储器单元的多个位线电压选项中的位线电压 强，弱或典型的记忆体。