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    METHODS AND SYSTEMS TO REDUCE LOCATION-BASED VARIATIONS IN SWITCHING CHARACTERISTICS OF 3D RERAM ARRAYS
    1.
    发明申请
    METHODS AND SYSTEMS TO REDUCE LOCATION-BASED VARIATIONS IN SWITCHING CHARACTERISTICS OF 3D RERAM ARRAYS 有权
    减少三维雷达阵列切换特性的基于位置变化的方法与系统

    公开(公告)号：US20140353573A1

    公开(公告)日：2014-12-04

    申请号：US14462374

    申请日：2014-08-18

    Applicant: SANDISK 3D LLC

    Inventor： Pankaj Kalra ,  Chandrasekhar Gorla ,  Masaaki Higashitani

    IPC: H01L27/24 ,  H01L21/3215 ,  H01L21/3205 ,  H01L49/02 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L28/20 ,  H01L29/78642 ,  H01L31/0547 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y02E10/52

    Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

    Abstract translation: 描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。 在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。 例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。 嵌入式电阻器可以包括存储器单元内的多晶硅层。 可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

    VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION
    2.
    发明申请
    VERTICAL BIT LINE TFT DECODER FOR HIGH VOLTAGE OPERATION 有权
    用于高电压操作的垂直位线TFT解码器

    公开(公告)号：US20140252454A1

    公开(公告)日：2014-09-11

    申请号：US13788990

    申请日：2013-03-07

    Applicant: SANDISK 3D LLC

    Inventor： Peter Rabkin ,  Masaaki Higashitani

    IPC: H01L27/105

    CPC classification number: H01L27/1052 ,  G11C13/0002 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/16

    Abstract: A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a channel extension, otherwise referred to as a gate/junction offset, is disclosed. The vertically oriented TFT selection device with channel extension serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device having a channel extension has a high breakdown voltage and low leakage current. The channel extension can be at the top junction or bottom junction of the TFT. Depending on whether the memory elements undergo a forward FORM or reverse FORM, either the bottom or top junction can have the channel extension. This provides for a high voltage junction where needed.

    Abstract translation: 公开了一种具有垂直取向的薄膜晶体管（TFT）选择装置的3D存储器阵列，其具有通道延伸，否则称为栅极/结偏移。 具有通道扩展的垂直取向的TFT选择装置用作3D存储器阵列中的垂直位线选择装置。 具有通道延伸的垂直TFT选择装置具有高击穿电压和低漏电流。 沟道延伸可以在TFT的顶部结或底部结。 取决于存储器元件是经历正向FORM还是反向FORM，底部或顶部结可以具有通道扩展。 这在需要时提供了高压接点。

    Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays
    3.
    发明授权
    Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays 有权
    减少3D ReRAM阵列开关特性的基于位置的变化的方法和系统

    公开(公告)号：US09318533B2

    公开(公告)日：2016-04-19

    申请号：US14462374

    申请日：2014-08-18

    Applicant: SANDISK 3D LLC

    Inventor： Pankaj Kalra ,  Chandrasekhar Gorla ,  Masaaki Higashitani

    IPC: H01L29/06 ,  H01L27/24 ,  H01L45/00 ,  H01L49/02 ,  H01L29/786

    CPC classification number: H01L27/2481 ,  H01L27/2409 ,  H01L28/20 ,  H01L29/78642 ,  H01L31/0547 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  Y02E10/52

    Abstract: Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.

    Abstract translation: 描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。 在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。 例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。 嵌入式电阻器可以包括存储器单元内的多晶硅层。 可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

    Method For Non-Volatile Memory Having 3D Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines
    7.
    发明申请
    Method For Non-Volatile Memory Having 3D Array of Read/Write Elements with Efficient Decoding of Vertical Bit Lines and Word Lines 有权
    具有有效解码垂直位线和字线的读/写元素的3D阵列的非易失性存储器的方法

    公开(公告)号：US20140043911A1

    公开(公告)日：2014-02-13

    申请号：US14057971

    申请日：2013-10-18

    Applicant: SANDISK 3D LLC

    Inventor： George Samachisa ,  Luca Fasoli ,  Masaaki Higashitani ,  Roy Edwin Scheuerlein

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

    Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

    Abstract translation: 存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。 存储元件响应于在其上施加的电压差而可逆地改变电导级。 三维阵列包括从基板到多层平面的两列立柱阵列。 第一组支柱线作为用于在每个平面上与字线阵列一起存取存储元件的局部位线。 第二组柱线连接到字线。 衬底上的金属线阵列可切换地连接到柱线以提供对第一和第二组柱线的接近，从而分别提供对三维阵列的位线和字线的访问。

    Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
    9.
    发明授权
    Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines 有权
    用于具有读/写元素的3D阵列的非易失性存储器的方法，其具有垂直位线和字线的有效解码

    公开(公告)号：US09245629B2

    公开(公告)日：2016-01-26

    申请号：US14057971

    申请日：2013-10-18

    Applicant: SANDISK 3D LLC

    Inventor： George Samachisa ,  Luca Fasoli ,  Masaaki Higashitani ,  Roy Edwin Scheuerlein

    IPC: G11C11/00 ,  G11C16/10 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    CPC classification number: G11C16/10 ,  G11C13/003 ,  G11C2213/71 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/06 ,  H01L45/065 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/149

    Abstract: A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

    Abstract translation: 存储元件的三维阵列形成在位于半导体衬底上方不同距离的多个平面层上。 存储元件响应于在其上施加的电压差而可逆地改变电导级。 三维阵列包括从基板到多层平面的两列立柱阵列。 第一组支柱线作为用于在每个平面上与字线阵列一起存取存储元件的局部位线。 第二组柱线连接到字线。 衬底上的金属线阵列可切换地连接到柱线以提供对第一和第二组柱线的接近，从而分别提供对三维阵列的位线和字线的访问。

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