Invention Grant
US09245629B2 Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
有权
用于具有读/写元素的3D阵列的非易失性存储器的方法,其具有垂直位线和字线的有效解码
- Patent Title: Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines
- Patent Title (中): 用于具有读/写元素的3D阵列的非易失性存储器的方法,其具有垂直位线和字线的有效解码
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Application No.: US14057971Application Date: 2013-10-18
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Publication No.: US09245629B2Publication Date: 2016-01-26
- Inventor: George Samachisa , Luca Fasoli , Masaaki Higashitani , Roy Edwin Scheuerlein
- Applicant: SANDISK 3D LLC
- Applicant Address: US CA Milpitas
- Assignee: SANDISK 3D LLC
- Current Assignee: SANDISK 3D LLC
- Current Assignee Address: US CA Milpitas
- Agency: Davis Wright Tremaine LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C16/10 ; G11C13/00 ; H01L27/24 ; H01L45/00

Abstract:
A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.
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