公开(公告)号：US20240203888A1

公开(公告)日：2024-06-20

申请号：US18430066

申请日：2024-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.

公开(公告)号：US20230187393A1

公开(公告)日：2023-06-15

申请号：US18168038

申请日：2023-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il CHOI ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/03 ,  H01L2224/17181 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/03825 ,  H01L2224/03914 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05082 ,  H01L2224/05015 ,  H01L2224/05027 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05644 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/06182 ,  H01L2224/06136 ,  H01L2224/02372 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US11004814B2

公开(公告)日：2021-05-11

申请号：US16244304

申请日：2019-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC: H01L23/00

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US12107063B2

公开(公告)日：2024-10-01

申请号：US17204313

申请日：2021-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Heewon Kim ,  Junyoung Park ,  Seong-Hoon Bae ,  Jin Ho An

IPC: H01L23/38 ,  H01L23/00 ,  H01L23/532 ,  H01L23/538

CPC classification number: H01L24/14 ,  H01L23/53238 ,  H01L23/5386 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13024

Abstract: A semiconductor package device may include a redistribution substrate and a semiconductor chip on a top surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern, which includes including a body portion and a protruding portion extended from the body portion to form a single object, an insulating layer covering a side surface of the body portion, and an outer coupling terminal on the protruding portion. The body portion may have a first diameter in a first direction parallel to the top surface of the redistribution substrate, and the protruding portion may have a second diameter in the first direction, which is smaller than the first diameter. A top surface of the protruding portion may be parallel to the first direction, and a side surface of the protruding portion may be inclined at an angle to a top surface of the body portion.

公开(公告)号：US11798872B2

公开(公告)日：2023-10-24

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Jeonggi Jin ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/182

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US10109665B2

公开(公告)日：2018-10-23

申请号：US15630063

申请日：2017-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Jin Lee ,  Kwangjin Moon ,  Seokho Kim ,  Sukchul Bang ,  Jin Ho An ,  Naein Lee

IPC: H01L27/146

Abstract: A semiconductor device includes a semiconductor substrate with first and second surfaces facing each other, an etch stop pattern in a trench formed in the first surface of the semiconductor substrate, a first insulating layer on the first surface of the semiconductor substrate, and a through via penetrating the semiconductor substrate and the first insulating layer. The etch stop pattern surrounds a portion of a lateral surface of the through via.

公开(公告)号：US08872351B2

公开(公告)日：2014-10-28

申请号：US13756833

申请日：2013-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangjin Moon ,  SuKyoung Kim ,  Kunsang Park ,  Byung Lyul Park ,  Sukchul Bang ,  Jin Ho An ,  Kyu-Ha Lee ,  Dosun Lee ,  Gilheyun Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/04 ,  H01L23/12 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13022 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract translation: 提供具有通孔的半导体器件及其制造方法。 所述方法可以包括形成至少部分地穿透基板的通孔，所述通孔具有设置在所述基板的顶表面上的入口，形成通孔绝缘层以保形地覆盖所述通孔的内表面，形成缓冲器 所述缓冲层由收缩性优于所述通孔绝缘层的材料形成，形成贯通电极以填充所述通孔，所述通孔设置在所述通孔绝缘层上， 与缓冲层一起凹陷基底的底表面以露出通孔。

公开(公告)号：US11742271B2

公开(公告)日：2023-08-29

申请号：US17306988

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuho Kang ,  Seong-Hoon Bae ,  Jin Ho An ,  Teahwa Jeong ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/182

Abstract: A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.

公开(公告)号：US11694978B2

公开(公告)日：2023-07-04

申请号：US17697830

申请日：2022-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Un-Byoung Kang ,  Jin Ho An ,  Jongho Lee ,  Jeonggi Jin ,  Atsushi Fujisaki

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05016 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155

Abstract: Semiconductor devices are provided. A semiconductor device includes an insulating layer and a conductive element in the insulating layer. The semiconductor device includes a first barrier pattern in contact with a surface of the conductive element and a surface of the insulating layer. The semiconductor device includes a second barrier pattern on the first barrier pattern. Moreover, the semiconductor device includes a metal pattern on the second barrier pattern. Related semiconductor packages are also provided.

公开(公告)号：US11637058B2

公开(公告)日：2023-04-25

申请号：US17099929

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Teahwa Jeong ,  Jeonggi Jin

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

Abstract: An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.