公开(公告)号：US20240145366A1

公开(公告)日：2024-05-02

申请号：US18141519

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Jumyong Park ,  Solji Song ,  Hyunchul Jung ,  Sanghoo Cho ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2224/08221 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/27416 ,  H01L2224/27444 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/182

Abstract: A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.

公开(公告)号：US11798872B2

公开(公告)日：2023-10-24

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Jeonggi Jin ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/182

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US11664312B2

公开(公告)日：2023-05-30

申请号：US17147661

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Seong-Hoon Bae ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/532 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/16227

Abstract: A semiconductor device includes a first semiconductor chip that includes a first conductive pad whose top surface is exposed; and a second semiconductor chip that includes a second conductive pad whose top surface is exposed and in contact with at least a portion of the top surface of the first conductive pad. The first semiconductor chip may include a first diffusion barrier in contact with a bottom surface of the first conductive pad, and a second diffusion barrier in contact with a lateral surface of the first conductive pad, and the first diffusion barrier and the second diffusion barrier may include different materials from each other.

公开(公告)号：US12224256B2

公开(公告)日：2025-02-11

申请号：US17711370

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

公开(公告)号：US12119306B2

公开(公告)日：2024-10-15

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US12009288B2

公开(公告)日：2024-06-11

申请号：US17230511

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US20230089399A1

公开(公告)日：2023-03-23

申请号：US17719721

申请日：2022-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Solji SONG ,  Junyun Kweon ,  Jumyong Park ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/78 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/16

Abstract: A semiconductor device includes a substrate, an insulating layer on a bottom surface of the substrate, a portion of a top surface of the insulating layer that faces the substrate being exposed outside a side surface of the substrate, a through via penetrating the substrate, an interconnection structure in the insulating layer, and a dummy pattern on the portion of the top surface of the insulating layer that is exposed by the substrate.

公开(公告)号：US20240321794A1

公开(公告)日：2024-09-26

申请号：US18679806

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

Abstract: A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US20240234103A1

公开(公告)日：2024-07-11

申请号：US18404423

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J2237/334

Abstract: A ring assembly is used in a semiconductor wafer etching device in which a plasma gas flow stream line is not uniform and which surrounds a wafer support plate supporting a semiconductor wafer. The ring assembly includes: an edge ring protruding from at least one side of the semiconductor wafer to have an upper surface higher than an upper surface of the semiconductor wafer; and a shadow ring movable up and down above the edge ring and configured to be tilted with respect to the semiconductor wafer.

公开(公告)号：US20240203888A1

公开(公告)日：2024-06-20

申请号：US18430066

申请日：2024-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/5383 ,  H01L21/4857 ,  H01L23/5386 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.