公开(公告)号：US11978688B2

公开(公告)日：2024-05-07

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/29

CPC classification number: H01L23/3192 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/293 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/0557 ,  H01L2224/05573

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20240145366A1

公开(公告)日：2024-05-02

申请号：US18141519

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Jumyong Park ,  Solji Song ,  Hyunchul Jung ,  Sanghoo Cho ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2224/08221 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/27416 ,  H01L2224/27444 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/182

Abstract: A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.

公开(公告)号：US11637058B2

公开(公告)日：2023-04-25

申请号：US17099929

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Teahwa Jeong ,  Jeonggi Jin

IPC: H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065

Abstract: An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.

公开(公告)号：US20240347510A1

公开(公告)日：2024-10-17

申请号：US18585468

申请日：2024-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeongil Lee ,  Byeongchan Kim ,  Unbyoung Kang ,  Jumyong Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49822 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03616 ,  H01L2224/05647 ,  H01L2224/13027 ,  H01L2224/81895 ,  H01L2225/06541 ,  H01L2924/1436

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a plurality of through electrodes, first bonding pads provided on a first surface of a first substrate, a first passivation layer provided on the first surface and exposing the first bonding pads, a polishing stop layer pattern provided on a second surface of the first substrate and exposing end portions of the plurality of through electrodes, and second bonding pads provided on the polishing stop layer pattern. The second semiconductor chip includes third bonding pads provided on a first surface of a second substrate, and a second passivation layer provided on the first surface of the second substrate and exposing the third bonding pads. The first bonding pads and the third bonding pads are directly bonded to each other.

公开(公告)号：US11798872B2

公开(公告)日：2023-10-24

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Jeonggi Jin ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/182

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US20210035878A1

公开(公告)日：2021-02-04

申请号：US16829227

申请日：2020-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

公开(公告)号：US09502274B2

公开(公告)日：2016-11-22

申请号：US14281880

申请日：2014-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Byung Lyul Park ,  Jumyong Park ,  Jisoon Park ,  Kyu-Ha Lee ,  Siyoung Choi

IPC: H01L21/673

CPC classification number: H01L21/6733 ,  H01L21/6732 ,  H01L21/67323 ,  H01L21/67326

Abstract: Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone.

Abstract translation: 本发明构思的实施例提供了具有一个或多个缓冲区的晶片装载器，以防止损坏装载在晶片装载器中的晶片。 晶片装载机可以包括从主体突出的多个装载部分，并被构造成沿着晶片的边缘布置在不同位置。 每个加载部分可以包括槽，其中可以插入晶片的边缘。 装载部分可以包括分别具有彼此面对以限定其间的凹槽的第一和第二内侧的第一和第二突起。 第一和第二内侧中的至少一个可以包括限定缓冲区的凹部。

公开(公告)号：US12224256B2

公开(公告)日：2025-02-11

申请号：US17711370

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

公开(公告)号：US12009288B2

公开(公告)日：2024-06-11

申请号：US17230511

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227

Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

公开(公告)号：US11996358B2

公开(公告)日：2024-05-28

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Jeonggi Jin ,  Jinho Chun

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.