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    SEMICONDUCTOR PACKAGE
    1.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250014958A1

    公开(公告)日：2025-01-09

    申请号：US18892965

    申请日：2024-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

    IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

    Abstract: A semiconductor package includes: a lower package including a lower semiconductor chip, a molding layer on a side surface of the lower semiconductor chip, a conductive post in the molding layer and having a concave top surface, a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution electrically connected the conductive post; and an upper package on the lower package, the upper package including an upper semiconductor chip. A first portion of an inner wall of the molding layer contacts a sidewall of the conductive post, and a second portion of the inner wall of the molding layer extends vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post.

    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210035878A1

    公开(公告)日：2021-02-04

    申请号：US16829227

    申请日：2020-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

    IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

    Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

    Semiconductor package
    5.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12142541B2

    公开(公告)日：2024-11-12

    申请号：US16829227

    申请日：2020-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

    IPC: H01L23/31 ,  H01L23/29 ,  H01L23/522

    Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

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