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    Semiconductor packages having first and second redistribution patterns
    1.
    发明授权
    Semiconductor packages having first and second redistribution patterns 有权

    公开(公告)号：US11996358B2

    公开(公告)日：2024-05-28

    申请号：US17364558

    申请日：2021-06-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： Ju-Il Choi ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Jeonggi Jin ,  Jinho Chun

    IPC分类号： H01L23/498

    CPC分类号： H01L23/49838 ,  H01L23/49822

    摘要： A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20210035878A1

    公开(公告)日：2021-02-04

    申请号：US16829227

    申请日：2020-03-25

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

    IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L23/522

    摘要： A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

    SEMICONDUCTOR PACKAGE
    9.
    发明公开
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20240347437A1

    公开(公告)日：2024-10-17

    申请号：US18630122

    申请日：2024-04-09

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jinho Chun

    IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/10

    CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

    摘要： A semiconductor package includes a redistribution substrate including a plurality of redistribution layers in an insulating layer and including an upper redistribution and a lower redistribution layer, a first pad structure; a second pad structure on the redistribution substrate and connected to the upper redistribution layer; a through-via extending to electrically connect the second pad structure and the plurality of redistribution layers; and a semiconductor chip, wherein the upper redistribution layer includes an upper pattern portion, a first upper pad portion connected to the first pad structure, and a second pad portion having an upper hole through which the through-via extends, the lower redistribution layer includes a lower pattern portion and a lower pad portion on at least one end of the lower pattern portion and having a lower hole through which the through-via extends, and the second pad structure includes a through-hole through which the through-via extends.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11538783B2

    公开(公告)日：2022-12-27

    申请号：US17088350

    申请日：2020-11-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

    IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/522

    摘要： A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.