公开(公告)号：US12021034B2

公开(公告)日：2024-06-25

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji Song ,  Byeongchan Kim ,  Jumyong Park ,  Jinho An ,  Chungsun Lee ,  Jeonggi Jin ,  Juil Choi

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US12218039B2

公开(公告)日：2025-02-04

申请号：US18311621

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

公开(公告)号：US20240266309A1

公开(公告)日：2024-08-08

申请号：US18637061

申请日：2024-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower

公开(公告)号：US20230111136A1

公开(公告)日：2023-04-13

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji Song ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US12224256B2

公开(公告)日：2025-02-11

申请号：US17711370

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

公开(公告)号：US11984420B2

公开(公告)日：2024-05-14

申请号：US18074134

申请日：2022-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US20230275011A1

公开(公告)日：2023-08-31

申请号：US18311621

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L23/49838 ,  H01L2224/16227

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.

公开(公告)号：US11978688B2

公开(公告)日：2024-05-07

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/29

CPC classification number: H01L23/3192 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L21/31053 ,  H01L21/3212 ,  H01L23/293 ,  H01L2224/05025 ,  H01L2224/05073 ,  H01L2224/0557 ,  H01L2224/05573

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20240145366A1

公开(公告)日：2024-05-02

申请号：US18141519

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Jumyong Park ,  Solji Song ,  Hyunchul Jung ,  Sanghoo Cho ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2224/08221 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/27416 ,  H01L2224/27444 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/182

Abstract: A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.

公开(公告)号：US11676887B2

公开(公告)日：2023-06-13

申请号：US17318227

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggi Jin ,  Gyuho Kang ,  Solji Song ,  Un-Byoung Kang ,  Ju-Il Choi

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package may include a redistribution substrate having a first surface and a second surface, opposite to each other, a semiconductor chip on the first surface of the redistribution substrate, and a solder pattern on the second surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern coupled to the solder pattern, a first redistribution pattern on the under-bump pattern, the first redistribution pattern including a first via portion and a first wire portion, and a first seed pattern between the under-bump pattern and the first redistribution pattern and on a side surface of the first via portion and a bottom surface of the first wire portion. A bottom surface of the first seed pattern may be at a level lower than a top surface of the under-bump pattern.