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    SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250087593A1

    公开(公告)日：2025-03-13

    申请号：US18581596

    申请日：2024-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Juil CHOI ,  Jusuk KANG ,  Jongho PARK ,  Jaeyoung LEE ,  Hyunju LEE ,  Wonho CHOI

    IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor package including a first semiconductor chip including a substrate having a front surface and a rear surface opposite to each other, front pads on the front surface, through-electrodes electrically connected to the front pads, passing through the substrate, and protruding onto the rear surface, and rear pads on the through-electrodes, a first dielectric layer covering at least a portion of the first semiconductor chip, the first dielectric layer surrounding, on the rear surface of the substrate, a portion of a side surface of each of the through-electrodes and a side surface of each of the rear pads, on the rear surface of the substrate, at least one first alignment structure within the first dielectric layer around the first semiconductor chip, and a second semiconductor chip on the first dielectric layer may be provided.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250038081A1

    公开(公告)日：2025-01-30

    申请号：US18734529

    申请日：2024-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongho PARK ,  Unbyoung KANG ,  Seonghoon BAE ,  Jaemok JUNG ,  Juil CHOI ,  Taeoh HA

    IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

    Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region and including first redistribution wirings, a semiconductor chip disposed on the first region of the lower redistribution wiring layer, a molding member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, electrically connected to the first redistribution wirings, and including first conductive pillars and second conductive pillars stacked on the first conductive pillars respectively, and an upper redistribution wiring layer disposed on the molding member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures. Each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length.

    SEMICONDUCTOR PACKAGE
    9.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230060115A1

    公开(公告)日：2023-02-23

    申请号：US17723552

    申请日：2022-04-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sechul PARK ,  Unbyoung KANG ,  Heewon KIM ,  Jongho PARK ,  Hyojin YUN ,  Juil CHOI

    IPC: H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package includes a first semiconductor chip on a base chip, a second semiconductor chip on the first semiconductor chip in a first direction, each of the first and second semiconductor chips including a TSV and being electrically connected to each other via the TSV, dam structures on the base chip and surrounding a periphery of the first semiconductor chip, a first adhesive film between the base chip and the first semiconductor chip, a portion of the first adhesive film filling a space between the first semiconductor chip and the dam structures, a second adhesive film between the first semiconductor chip and the second semiconductor chip, a portion of the second adhesive film overlapping the dam structures in the first direction, and an encapsulant encapsulating a portion of each of the dam structures, the first semiconductor chip, and the second semiconductor chip.

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