公开(公告)号：US20250038081A1

公开(公告)日：2025-01-30

申请号：US18734529

申请日：2024-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Unbyoung KANG ,  Seonghoon BAE ,  Jaemok JUNG ,  Juil CHOI ,  Taeoh HA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region and including first redistribution wirings, a semiconductor chip disposed on the first region of the lower redistribution wiring layer, a molding member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, electrically connected to the first redistribution wirings, and including first conductive pillars and second conductive pillars stacked on the first conductive pillars respectively, and an upper redistribution wiring layer disposed on the molding member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures. Each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length.