公开(公告)号：US20240071899A1

公开(公告)日：2024-02-29

申请号：US18450836

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuho KANG ,  Hyungjun PARK ,  Seonghoon BAE ,  Sanghyuck OH ,  Kwangok JEONG ,  Juil CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49866 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/105 ,  H01L24/16

Abstract: Provided is a semiconductor package. The semiconductor package including a redistribution structure including a plurality of redistribution conductive patterns, a plurality of conductive vias connected to at least one of the plurality of redistribution conductive patterns, a plurality of lower pads connected to the plurality of conductive vias, and a plurality of redistribution insulation layers and the plurality of redistribution conductive patterns alternating each other, a semiconductor chip arranged on the redistribution structure, and an external connection terminal attached to the plurality of lower surface pads of the redistribution structure, wherein each of the plurality of redistribution conductive patterns includes a metal layer including copper and a skin layer arranged on an upper surface of the metal layer and including copper and nickel, may be provided.

公开(公告)号：US20250038081A1

公开(公告)日：2025-01-30

申请号：US18734529

申请日：2024-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Unbyoung KANG ,  Seonghoon BAE ,  Jaemok JUNG ,  Juil CHOI ,  Taeoh HA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region and including first redistribution wirings, a semiconductor chip disposed on the first region of the lower redistribution wiring layer, a molding member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, electrically connected to the first redistribution wirings, and including first conductive pillars and second conductive pillars stacked on the first conductive pillars respectively, and an upper redistribution wiring layer disposed on the molding member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures. Each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length.