公开(公告)号：US20240071899A1

公开(公告)日：2024-02-29

申请号：US18450836

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuho KANG ,  Hyungjun PARK ,  Seonghoon BAE ,  Sanghyuck OH ,  Kwangok JEONG ,  Juil CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49866 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/105 ,  H01L24/16

Abstract: Provided is a semiconductor package. The semiconductor package including a redistribution structure including a plurality of redistribution conductive patterns, a plurality of conductive vias connected to at least one of the plurality of redistribution conductive patterns, a plurality of lower pads connected to the plurality of conductive vias, and a plurality of redistribution insulation layers and the plurality of redistribution conductive patterns alternating each other, a semiconductor chip arranged on the redistribution structure, and an external connection terminal attached to the plurality of lower surface pads of the redistribution structure, wherein each of the plurality of redistribution conductive patterns includes a metal layer including copper and a skin layer arranged on an upper surface of the metal layer and including copper and nickel, may be provided.

公开(公告)号：US20230142267A1

公开(公告)日：2023-05-11

申请号：US17979233

申请日：2022-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangok JEONG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02373

Abstract: A semiconductor package includes a lower redistribution structure including a wiring layer, and a via connected to the wiring layer, a connection substrate on the lower redistribution structure, the connection substrate including a base layer, lower conductive patterns in the base layer, first upper conductive patterns disposed on the base layer, the first upper conductive patterns including an upper pad, and a second upper conductive pattern disposed on the upper pad, a semiconductor chip disposed on the lower redistribution structure and disposed in a cavity of the connection substrate, an encapsulant covering the lower redistribution structure, the connection substrate and the semiconductor chip, and an upper redistribution structure on the encapsulant. The upper redistribution structure includes a redistribution via connected to the second upper conductive pattern.

公开(公告)号：US20180350838A1

公开(公告)日：2018-12-06

申请号：US16043236

申请日：2018-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L21/66 ,  G06F17/50 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/092 ,  H01L27/02 ,  G03F1/36 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20170062475A1

公开(公告)日：2017-03-02

申请号：US15282206

申请日：2016-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  G03F1/36 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20200212069A1

公开(公告)日：2020-07-02

申请号：US16817094

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L27/11582 ,  G03F1/36 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327 ,  G06F30/30

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20170062403A1

公开(公告)日：2017-03-02

申请号：US15238912

申请日：2016-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/02 ,  G03F1/36 ,  H01L21/8238 ,  G06F17/50 ,  H01L21/66 ,  H01L27/092

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract translation: 半导体器件包括包括第一有源区和第二有源区的衬底，第一有源区具有不同于第二有源区的导电类型的导电类型，并且第一有源区与第二有源区间隔开 区域，第一方向上延伸的栅电极，与第一有源区和第二有源区交叉的栅电极，设置在第一有源区的上部的第一浅隔离图案，第一浅隔离图案延伸 以及设置在第二有源区的上部的深隔离图案，深隔离图案沿第一方向延伸，深隔离图案将第二有源区分割成第一区域和第二区域。