公开(公告)号：US20240203855A1

公开(公告)日：2024-06-20

申请号：US18356721

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemok JUNG ,  Un-Byoung KANG ,  Dowan KIM ,  Sung Keun PARK ,  Jongho PARK ,  Ju-Il CHOI

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/565 ,  H01L21/76811 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/08055 ,  H01L2224/08155 ,  H01L2224/32146 ,  H01L2224/32235 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/182

Abstract: An embodiment provides a semiconductor package including: a first redistribution layer substrate; a semiconductor chip on the first redistribution layer substrate; a coupling member on the first redistribution layer substrate, wherein the coupling member is spaced apart from the semiconductor chip; an encapsulant on the first redistribution layer substrate, the semiconductor chip, and the coupling member; and a second redistribution layer substrate on the encapsulant, wherein the coupling member includes a vertical wire and a metal portion extending around the vertical wire, and wherein a first end of the coupling member is electrically connected to the first redistribution layer substrate, and a second end of the coupling member is electrically connected to the second redistribution layer substrate.

公开(公告)号：US20250038081A1

公开(公告)日：2025-01-30

申请号：US18734529

申请日：2024-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Unbyoung KANG ,  Seonghoon BAE ,  Jaemok JUNG ,  Juil CHOI ,  Taeoh HA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region and including first redistribution wirings, a semiconductor chip disposed on the first region of the lower redistribution wiring layer, a molding member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, electrically connected to the first redistribution wirings, and including first conductive pillars and second conductive pillars stacked on the first conductive pillars respectively, and an upper redistribution wiring layer disposed on the molding member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures. Each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length.

公开(公告)号：US20240213223A1

公开(公告)日：2024-06-27

申请号：US18516367

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemok JUNG ,  Dowan KIM ,  Sungkeun PARK ,  Jongho PARK ,  Juil CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/08056 ,  H01L2224/08245 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06544 ,  H01L2924/181

Abstract: A semiconductor package includes a first redistribution wiring layer having a first region and a second region surrounding the first region, a semiconductor chip disposed on the first region of the first redistribution wiring layer, a sealing member covering the semiconductor chip on the first redistribution wiring layer, vertical conductive wires penetrating the sealing member on the second region of the first redistribution wiring layer, a second redistribution wiring layer disposed on the sealing member and including second redistribution wirings electrically connected to the vertical conductive wires, and bonding pads provided on an upper surface of the first redistribution wiring layer or a lower surface of the second redistribution wiring layer, each bonding pad having a concavo-convex pattern on an upper surface of the bonding pad. The vertical conductive wires are bonded to the concavo-convex patterns of the bonding pads, respectively.

公开(公告)号：US20240079394A1

公开(公告)日：2024-03-07

申请号：US18366054

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil CHOI ,  Jongho PARK ,  Sanghyuck OH ,  Jaeyoung LEE ,  Jaemok JUNG ,  Hongseo HEO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H10B80/00 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package may include a first redistribution structure, a first semiconductor chip on the first redistribution structure, a first molding layer covering the first semiconductor chip, first connection structures on the first redistribution structure and extending in a vertical direction while passing through the first molding layer, a second redistribution structure on the first semiconductor chip, a second semiconductor chip on the second redistribution structure, and a metal layer on the second semiconductor chip. The metal layer may be in contact with an upper surface of the second semiconductor chip.