公开(公告)号：US20210398913A1

公开(公告)日：2021-12-23

申请号：US17466750

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon OH ,  Sukho LEE ,  Jusuk KANG

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.

公开(公告)号：US20250087593A1

公开(公告)日：2025-03-13

申请号：US18581596

申请日：2024-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil CHOI ,  Jusuk KANG ,  Jongho PARK ,  Jaeyoung LEE ,  Hyunju LEE ,  Wonho CHOI

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package including a first semiconductor chip including a substrate having a front surface and a rear surface opposite to each other, front pads on the front surface, through-electrodes electrically connected to the front pads, passing through the substrate, and protruding onto the rear surface, and rear pads on the through-electrodes, a first dielectric layer covering at least a portion of the first semiconductor chip, the first dielectric layer surrounding, on the rear surface of the substrate, a portion of a side surface of each of the through-electrodes and a side surface of each of the rear pads, on the rear surface of the substrate, at least one first alignment structure within the first dielectric layer around the first semiconductor chip, and a second semiconductor chip on the first dielectric layer may be provided.