公开(公告)号：US20230111136A1

公开(公告)日：2023-04-13

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji Song ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20210335688A1

公开(公告)日：2021-10-28

申请号：US17035145

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji SONG ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20240312894A1

公开(公告)日：2024-09-19

申请号：US18668974

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20220037248A1

公开(公告)日：2022-02-03

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.