公开(公告)号：US20250105216A1

公开(公告)日：2025-03-27

申请号：US18808787

申请日：2024-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun Jee ,  Jihwan Suh ,  Hyunchul Jung

IPC: H01L25/065 ,  H01L23/00

Abstract: Provided is a semiconductor package and method of manufacturing same, the semiconductor package including: a first semiconductor chip; a chip stacked structure on the first semiconductor chip, the chip stacked structure including a plurality of second semiconductor chips; a third semiconductor chip on the chip stacked structure; an adhesive layer between the chip stacked structure and the third semiconductor chip; and a first pad pattern on a lower surface of the third semiconductor chip, wherein the adhesive layer surrounds the first pad pattern and the adhesive layer is between the first pad pattern and the chip stacked structure.

公开(公告)号：US20240234103A1

公开(公告)日：2024-07-11

申请号：US18404423

申请日：2024-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01J37/32

CPC classification number: H01J37/32642 ,  H01J37/32715 ,  H01J2237/334

Abstract: A ring assembly is used in a semiconductor wafer etching device in which a plasma gas flow stream line is not uniform and which surrounds a wafer support plate supporting a semiconductor wafer. The ring assembly includes: an edge ring protruding from at least one side of the semiconductor wafer to have an upper surface higher than an upper surface of the semiconductor wafer; and a shadow ring movable up and down above the edge ring and configured to be tilted with respect to the semiconductor wafer.

公开(公告)号：US11652076B2

公开(公告)日：2023-05-16

申请号：US17736536

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeho Ko ,  Daehee Lee ,  Hyunchul Jung

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L24/24 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/03462 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/245 ,  H01L2224/24101 ,  H01L2224/24155 ,  H01L2224/82101 ,  H01L2224/82106

Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

公开(公告)号：US11355467B2

公开(公告)日：2022-06-07

申请号：US16983296

申请日：2020-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeho Ko ,  Daehee Lee ,  Hyunchul Jung

IPC: H01L23/31 ,  H01L23/00

Abstract: A semiconductor device may include a semiconductor chip in an encapsulant. A first insulation layer may be disposed on the encapsulant and the semiconductor chip. A horizontal wiring and a primary pad may be disposed on the first insulation layer. A secondary pad may be disposed on the primary pad. A second insulation layer covering the horizontal wiring may be disposed on the first insulation layer. A solder ball may be disposed on the primary pad and the secondary pad. The primary pad may have substantially the same thickness as a thickness of the horizontal wiring.

公开(公告)号：US20240145366A1

公开(公告)日：2024-05-02

申请号：US18141519

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoon Oh ,  Jumyong Park ,  Solji Song ,  Hyunchul Jung ,  Sanghoo Cho ,  Hyunsu Hwang

IPC: H01L23/498 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76898 ,  H01L24/08 ,  H01L24/09 ,  H01L24/27 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2224/08221 ,  H01L2224/0903 ,  H01L2224/09181 ,  H01L2224/27416 ,  H01L2224/27444 ,  H01L2224/32145 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2225/06541 ,  H01L2924/182

Abstract: A method of manufacturing a semiconductor package including forming a first semiconductor chip including a first substrate having a first and second surfaces and forming a second semiconductor chip including a second substrate having third and fourth surfaces. Arranging the second semiconductor chip on the first semiconductor chip such that bonding pads that are exposed from the front surface of the second semiconductor chip are bonded to conductive pads that are exposed from the rear surface of the first semiconductor chip. Forming a first through via having a first diameter and that penetrates the first substrate. Forming an insulating layer that exposes a first end of the first through via on the second surface of the first substrate, etching the first end of the first through via to a first depth, and applying a conductive material to the first end to form the conductive pad having a second diameter.

公开(公告)号：US20240237349A1

公开(公告)日：2024-07-11

申请号：US18464348

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Un-Byoung Kang ,  Jumyong Park ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H10B43/27 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A three-dimensional semiconductor memory device may include a bottom structure and a top structure thereon. The bottom structure may include a semiconductor substrate including a cell array region and a connection region extending therefrom, and a first stack including first gate electrodes and first interlayer insulating layers alternately stacked on the semiconductor substrate. The top structure may include a second stack including second gate electrodes and second interlayer insulating layers alternately stacked on the first stack. Respective lengths of the first gate electrodes in a second direction may decrease as a distance in a first direction increases, and respective lengths of the second gate electrodes in the second direction may increase as a distance in the first direction increases. The first direction may be perpendicular to a bottom surface of the semiconductor substrate, and the second direction may be parallel to the bottom surface of the semiconductor substrate.

公开(公告)号：US20240162104A1

公开(公告)日：2024-05-16

申请号：US18462010

申请日：2023-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsu Hwang ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Hyunchul Jung ,  Sanghoo Cho

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/3107 ,  H01L21/78 ,  H01L23/5226 ,  H01L24/08 ,  H01L2224/08145

Abstract: A semiconductor device may include a substrate, one or more front pads disposed on a front surface of the substrate, and a circuit layer including an insulating layer and at least one interconnection electrically connected to the one or more front pads. In some embodiments, the circuit layer may be disposed between the one or more front pads and the substrate. In some embodiments, a side surface of the circuit layer may include a burr that protrudes a height that is below a level of a front surface of the circuit layer. Additionally or alternatively, the burr may form a step portion in the circuit layer.

公开(公告)号：US20230420397A1

公开(公告)日：2023-12-28

申请号：US18322570

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsu Hwang ,  Unbyoung Kang ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Hyunchul Jung

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/48 ,  H01L25/0657 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/05082 ,  H01L2224/05561 ,  H01L2224/05567 ,  H01L2224/05025

Abstract: A includes a semiconductor substrate, a pad insulating layer disposed on the semiconductor substrate, a through electrode structure that partially penetrates the semiconductor substrate but does not penetrate the pad insulating layer, an insulating liner that at least partially surrounds the through electrode structure, an insulating sidewall that penetrates the pad insulating layer, a part of the semiconductor substrate and at least a part of the insulating liner, and includes a pad hole formed therein, and a bonding pad structure disposed on the pad insulating layer and that fills the pad hole, and contacts the through electrode structure