公开(公告)号：US20240321794A1

公开(公告)日：2024-09-26

申请号：US18679806

申请日：2024-05-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

摘要： A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US12021034B2

公开(公告)日：2024-06-25

申请号：US17198359

申请日：2021-03-11

申请人： Samsung Electronics Co., Ltd.

发明人： Solji Song ,  Byeongchan Kim ,  Jumyong Park ,  Jinho An ,  Chungsun Lee ,  Jeonggi Jin ,  Juil Choi

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

摘要： A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US08872306B2

公开(公告)日：2014-10-28

申请号：US13797655

申请日：2013-03-12

申请人： Samsung Electronics Co., Ltd.

发明人： Jeonggi Jin ,  Jeong-woo Park ,  Ju-il Choi

IPC分类号： H01L23/525 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/29

CPC分类号： H01L23/5256 ,  H01L23/293 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05541 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552 ,  H01L2924/00

摘要： Provided are electrical connection structures and methods of fabricating the same. The structures may include a substrate including a bonding pad region provided with a bonding pad and a fuse region provided with a fuse, an insulating layer provided on the substrate and including a bonding pad opening exposing the bonding pad and a fuse opening exposing the fuse region, a connection terminal provided in the bonding pad region and electrically connected to the bonding pad, and a protection layer provided on the insulating layer including a first protection layer provided within the bonding pad region and a second protection layer in the fuse opening.

摘要翻译： 提供电连接结构及其制造方法。 该结构可以包括：衬底，其包括具有接合焊盘的接合焊盘区域和设置有保险丝的熔断器区域，设置在衬底上的绝缘层，并且包括露出焊盘的焊盘开口和暴露熔丝区域的保险丝开口 设置在所述焊盘区域中并且电连接到所述焊盘的连接端子，以及设置在所述绝缘层上的保护层，所述保护层包括设置在所述焊盘区域内的第一保护层和所述熔丝开口中的第二保护层。

公开(公告)号：US12027482B2

公开(公告)日：2024-07-02

申请号：US17568355

申请日：2022-01-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonggi Jin ,  Gyuho Kang ,  Unbyoung Kang ,  Heewon Kim ,  Jumyong Park ,  Hyunsu Hwang

IPC分类号： H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L24/08 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/02251 ,  H01L2224/05009 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/08146

摘要： A semiconductor chip includes: a semiconductor substrate; a pad insulating layer on the semiconductor substrate; a through electrode which penetrates the semiconductor substrate and the pad insulating layer and includes a conductive plug and a conductive barrier layer surrounding a sidewall of the conductive plug; and a bonding pad which surrounds a sidewall of the through electrode and is spaced apart from the conductive plug with the conductive barrier layer disposed therebetween.

公开(公告)号：US11538783B2

公开(公告)日：2022-12-27

申请号：US17088350

申请日：2020-11-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/522

摘要： A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

公开(公告)号：US11476176B2

公开(公告)日：2022-10-18

申请号：US17035145

申请日：2020-09-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jumyong Park ,  Solji Song ,  Jinho An ,  Jeonggi Jin ,  Jinho Chun ,  Juil Choi

IPC分类号： H01L29/40 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/321 ,  H01L23/29 ,  H01L21/3105

摘要： A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US11444014B2

公开(公告)日：2022-09-13

申请号：US16830361

申请日：2020-03-26

申请人： Samsung Electronics Co., Ltd.

发明人： Jinho Chun ,  Jin Ho An ,  Teahwa Jeong ,  Jeonggi Jin ,  Ju-Il Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/49 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

摘要： There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

公开(公告)号：US20240266309A1

公开(公告)日：2024-08-08

申请号：US18637061

申请日：2024-04-16

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeonggi Jin ,  Solji Song ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L24/14 ,  H01L23/5226 ,  H01L2224/13008 ,  H01L2224/13009 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/16146

摘要： A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower

公开(公告)号：US11798872B2

公开(公告)日：2023-10-24

申请号：US17308643

申请日：2021-05-05

申请人： Samsung Electronics Co., Ltd.

发明人： Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Jeonggi Jin ,  Hyunsu Hwang

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L23/49822 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16235 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/182

摘要： Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US20210035878A1

公开(公告)日：2021-02-04

申请号：US16829227

申请日：2020-03-25

申请人： Samsung Electronics Co., Ltd.

发明人： Jeonggi Jin ,  Jumyong Park ,  Jinho An ,  Taehwa Jeong ,  Jinho Chun ,  Juil Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/31 ,  H01L23/29 ,  H01L23/522

摘要： A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.