公开(公告)号：US11728297B2

公开(公告)日：2023-08-15

申请号：US17325384

申请日：2021-05-20

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L24/05 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/0362 ,  H01L2224/03416 ,  H01L2224/03418 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/03831 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05085 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05562 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/1312 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8181 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/15311 ,  H01L2224/05171 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2224/13111 ,  H01L2924/01079 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2224/13111 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13113 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13139 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13118 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2224/13116 ,  H01L2924/013 ,  H01L2924/00014

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US11581279B2

公开(公告)日：2023-02-14

申请号：US17229023

申请日：2021-04-13

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC分类号： H01L23/00

摘要： Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

公开(公告)号：US11018101B2

公开(公告)日：2021-05-25

申请号：US16398888

申请日：2019-04-30

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US10325869B2

公开(公告)日：2019-06-18

申请号：US15870044

申请日：2018-01-12

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer

公开(公告)号：US08987869B2

公开(公告)日：2015-03-24

申请号：US13738728

申请日：2013-01-10

申请人： Samsung Electronics Co., Ltd.

发明人： Jeong-gi Jin ,  Jeong-woo Park ,  Ju-il Choi

IPC分类号： H01L23/52 ,  H01L29/40 ,  H01L29/82 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/6835 ,  H01L2224/03828 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1161 ,  H01L2224/1162 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/81011 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole.

摘要翻译： 一种集成电路器件，包括在衬底上的层间绝缘层，层间绝缘层上的导线层和穿过硅通孔（TSV）的接触图案，所述接触图形具有接触所述导线层的端部并且从通孔内部一体地延伸 通过层间绝缘层和基板形成到通孔的外部。

公开(公告)号：US08816499B2

公开(公告)日：2014-08-26

申请号：US13826694

申请日：2013-03-14

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Jeong-Woo Park ,  Jeonggi Jin ,  Yeun-Sang Park

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/12 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13183 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552

摘要： Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.

摘要翻译： 提供电互连及其制造方法。 电互连可以包括：衬底，其包括接合焊盘，与接合焊盘电连接的焊球，焊盘上的焊料支撑体，填充焊料支撑体的焊球的一部分，以及焊接垫和 所述焊料支撑体，所述金属层的电离倾向低于所述接合焊盘。

公开(公告)号：US20210272918A1

公开(公告)日：2021-09-02

申请号：US17325384

申请日：2021-05-20

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

摘要： A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

公开(公告)号：US10763163B2

公开(公告)日：2020-09-01

申请号：US16242122

申请日：2019-01-08

申请人： Samsung Electronics Co., Ltd.

发明人： Su-jeong Park ,  Dong-chan Lim ,  Kwang-jin Moon ,  Ju-bin Seo ,  Ju-il Choi ,  Atsushi Fujisaki

IPC分类号： H01L23/48 ,  H01L21/768

摘要： An integrated circuit device includes a substrate, a landing pad on the substrate, and a through-via structure passing through the substrate and connected to the landing pad. The through-via structure may include a conductive plug, a first conductive barrier layer covering a sidewall and a lower surface of the conductive plug, and a second conductive barrier layer covering a sidewall of the first conductive barrier layer.

公开(公告)号：US20130313707A1

公开(公告)日：2013-11-28

申请号：US13826694

申请日：2013-03-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ju-il Choi ,  Jeong-woo Park ,  Jeonggi Jin ,  Yeun-Sang Park

IPC分类号： H01L23/00

CPC分类号： H01L24/12 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13183 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552

摘要： Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.

摘要翻译： 提供电互连及其制造方法。 电互连可以包括：衬底，其包括接合焊盘，与接合焊盘电连接的焊球，焊盘上的焊料支撑体，填充焊料支撑体的焊球的一部分，以及在焊盘和焊盘之间的金属层 所述焊料支撑体，所述金属层的电离倾向低于所述接合焊盘。

公开(公告)号：US20190385964A1

公开(公告)日：2019-12-19

申请号：US16244304

申请日：2019-01-10

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Kwangjin Moon ,  Sujeong Park ,  JuBin Seo ,  Jin Ho An ,  Dong-chan Lim ,  Atsushi Fujisaki

IPC分类号： H01L23/00

摘要： Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.