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    SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210272918A1

    公开(公告)日：2021-09-02

    申请号：US17325384

    申请日：2021-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

    Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

    Integrated Circuit Devices Having Through-Silicon Via Structures and Methods of Manufacturing the Same
    5.
    发明申请
    Integrated Circuit Devices Having Through-Silicon Via Structures and Methods of Manufacturing the Same 有权
    具有通硅结构的集成电路器件及其制造方法

    公开(公告)号：US20170053872A1

    公开(公告)日：2017-02-23

    申请号：US15235608

    申请日：2016-08-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-jin Lee ,  Byung-lyul Park ,  Jin-ho An

    IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00

    CPC classification number: H01L23/5384 ,  H01L21/76841 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/18161

    Abstract: Integrated circuit (IC) devices are provided including a substrate having a first sidewall defining a first through hole that is a portion of a through-silicon via (TSV) space, an interlayer insulating layer having a second sidewall and a protrusion, wherein the second sidewall defines a second through hole providing another portion of the TSV space and communicating with the first through hole, and the protrusion protrudes toward the inside of the TSV space and defines an undercut region in the first through hole, a TSV structure penetrating the substrate and the interlayer insulating layer and extending through the first through hole and the second through hole, and a via insulating layer surrounding the TSV structure in the first through hole and the second through hole.

    Abstract translation: 提供集成电路（IC）装置，其包括具有限定作为穿硅通孔（TSV）空间的一部分的第一通孔的第一侧壁的衬底，具有第二侧壁和突起的层间绝缘层，其中第二通孔 侧壁限定提供TSV空间的另一部分并与第一通孔连通的第二通孔，并且突出部朝向TSV空间的内部突出，并且在第一通孔中限定底切区域，穿透基板的TSV结构， 所述层间绝缘层延伸穿过所述第一通孔和所述第二通孔;以及通孔绝缘层，其围绕所述第一通孔和所述第二通孔中的TSV结构。

    SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES
    6.
    发明申请
    SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190259718A1

    公开(公告)日：2019-08-22

    申请号：US16398888

    申请日：2019-04-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/48

    Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

    SEMICONDUCTOR CHIP
    9.
    发明申请
    SEMICONDUCTOR CHIP 审中-公开

    公开(公告)号：US20200066666A1

    公开(公告)日：2020-02-27

    申请号：US16668146

    申请日：2019-10-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-jin Lee

    IPC: H01L23/00 ,  H01L23/31

    Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

    SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES
    10.
    发明申请
    SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190027450A1

    公开(公告)日：2019-01-24

    申请号：US15870044

    申请日：2018-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ju-il Choi ,  Kwang-jin Moon ,  Ju-bin Seo ,  Dong-chan Lim ,  Atsushi Fujisaki ,  Ho-jin Lee

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

    Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

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