公开(公告)号：US10381326B2

公开(公告)日：2019-08-13

申请号：US14289483

申请日：2014-05-28

申请人： Invensas Corporation

发明人： Charles G. Woychik ,  Arkalgud R. Sitaram ,  Andrew Cao ,  Bong-Sub Lee

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L21/56 ,  H01L23/373 ,  H01L23/367 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L21/683 ,  H01L25/03 ,  H01L25/18

摘要： A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

公开(公告)号：US09887166B2

公开(公告)日：2018-02-06

申请号：US15165837

申请日：2016-05-26

申请人： Invensas Corporation

发明人： Rajesh Katkar ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram ,  Charles G. Woychik

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L21/66 ,  H01L21/78 ,  H01L23/10 ,  H01L23/14 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L21/784 ,  H01L25/18

CPC分类号： H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/16176 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

公开(公告)号：US09865548B2

公开(公告)日：2018-01-09

申请号：US15158963

申请日：2016-05-19

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC分类号： H01L21/00 ,  H01L23/49 ,  H01L21/76 ,  H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

摘要： An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

公开(公告)号：US20170317019A1

公开(公告)日：2017-11-02

申请号：US15651826

申请日：2017-07-17

申请人： INVENSAS CORPORATION

发明人： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC分类号： H01L23/498 ,  H01L23/10 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/16

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

摘要： An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US09741649B2

公开(公告)日：2017-08-22

申请号：US14586580

申请日：2014-12-30

申请人： Invensas Corporation

发明人： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Guilian Gao

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/16 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/10 ,  H01L23/13

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/56 ,  H01L23/10 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/162 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16195 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83

摘要： An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.

公开(公告)号：US09741620B2

公开(公告)日：2017-08-22

申请号：US14749529

申请日：2015-06-24

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Guilian Gao ,  Liang Wang ,  Hong Shen ,  Arkalgud R. Sitaram

IPC分类号： H01L21/00 ,  H01L21/70 ,  H01L21/82 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

摘要： A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

公开(公告)号：US20170099474A1

公开(公告)日：2017-04-06

申请号：US15280661

申请日：2016-09-29

申请人： Invensas Corporation

发明人： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC分类号： H04N9/43 ,  H04N9/097 ,  H04N9/04 ,  G06T1/20 ,  H04N5/374 ,  H01L31/0232 ,  G02B27/10 ,  H01L27/146 ,  H01L31/0304 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/032 ,  H04N5/33 ,  H04N9/76

CPC分类号： H04N9/43 ,  G02B27/1013 ,  G06T1/20 ,  H01L27/1462 ,  H01L27/14634 ,  H01L27/14645 ,  H01L27/1465 ,  H01L27/14685 ,  H01L27/1469 ,  H01L31/02322 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/332 ,  H04N5/374 ,  H04N9/045 ,  H04N9/097 ,  H04N9/76

摘要： HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

公开(公告)号：US20170040237A1

公开(公告)日：2017-02-09

申请号：US15265148

申请日：2016-09-14

申请人： Invensas Corporation

发明人： Hong SHEN ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC分类号： H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

摘要翻译： 具有集成电路的模具（110）附接到布线基板（120），可能是插入件，并且被附接到布线基板的保护基板（410）保护。 模具位于保护衬底中的空腔中（模具可能突出出腔体）。 在一些实施例中，每个空腔表面在模具上施加压力以加强模具与布线基板的机械连接，以在模具和环境（或散热器）之间提供良好的导热性以抵抗模具翘曲，并且可能 减小垂直尺寸。 保护衬底可以具有或不具有连接到管芯或布线衬底的其自身的电路。 还提供其他功能。

公开(公告)号：US20160329301A1

公开(公告)日：2016-11-10

申请号：US15164179

申请日：2016-05-25

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC分类号： H01L25/065 ,  H01L23/498 ,  C25F3/14 ,  H01L21/48 ,  H01L23/00 ,  C25F3/12 ,  H01L23/367 ,  H01L23/373

CPC分类号： H01L25/0655 ,  C25F3/12 ,  C25F3/14 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/367 ,  H01L23/3733 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15701 ,  H01L2924/15724 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H05K1/0212 ,  H05K1/115 ,  H05K3/07 ,  H05K2201/10378

摘要： A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region.

公开(公告)号：US20160284672A1

公开(公告)日：2016-09-29

申请号：US15174338

申请日：2016-06-06

申请人： Invensas Corporation

发明人： Rajesh Katkar ,  Arkalgud R. Sitaram ,  Cyprian Emeka Uzoh

IPC分类号： H01L25/065 ,  H01L23/367

CPC分类号： H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

摘要： An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

摘要翻译： 装置一般涉及三维堆叠集成电路。 在这种装置中，三维堆叠集成电路具有至少第一管芯和第二管芯，使用管芯到管芯互连彼此互连。 第一管芯的衬底具有至少一个热通孔结构，其从衬底的下表面朝向衬底的阱延伸，而不延伸到阱并且不延伸通过衬底。 所述至少一个热通孔结构的第一端至少足够靠近所述衬底的阱，用于将热量传导出来。 衬底具有从衬底的下表面延伸到衬底的上表面的至少一个穿过衬底通孔结构。 所述至少一个热通孔结构的第二端与所述第二管芯的至少一个通孔通孔结构耦合以进行导热。