公开(公告)号：US20170301670A1

公开(公告)日：2017-10-19

申请号：US15641336

申请日：2017-07-05

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia Chang Hsu ,  Chun-Hsien Lin

IPC分类号： H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

摘要： A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US09748233B2

公开(公告)日：2017-08-29

申请号：US14873223

申请日：2015-10-02

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chia Chang Hsu ,  Chun-Hsien Lin

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40

CPC分类号： H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

摘要： A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US20170047282A1

公开(公告)日：2017-02-16

申请号：US14822597

申请日：2015-08-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Zhiguo SUN ,  Qiang FANG ,  Huang LIU ,  Haigou HUANG ,  Jiehui SHU ,  Jin Ping LIU

IPC分类号： H01L23/528 ,  H01L21/321 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3065 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/3065 ,  H01L21/321 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76853 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53266

摘要： Reducing liner corrosion during metallization of semiconductor devices at BEOL includes providing a starting metallization structure, the structure including a bottom layer of dielectric material with a via therein, a liner lining the via and extending over upper edges thereof, the lined via over filled with a conductive material, recessing the conductive material down to the liner, further selectively recessing the conductive material below the upper edges of the via without damaging the liner, and forming a cap of the liner material on the conductive material.

摘要翻译： 在BEOL的半导体器件的金属化期间减少衬里腐蚀包括提供起始金属化结构，该结构包括介电材料的底层，其中具有通孔，衬套衬套通孔并在其上边缘延伸的衬里，衬里通孔填充有 导电材料将导电材料向下凹入衬垫，进一步选择性地使导电材料在通孔的上边缘下方凹陷，而不损坏衬垫，并且在导电材料上形成衬垫材料的帽。

公开(公告)号：US08709939B2

公开(公告)日：2014-04-29

申请号：US13633562

申请日：2012-10-02

申请人： Semiconductor Technology Academic Research Center ,  National University Corporation Tohoku University

发明人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

IPC分类号： H01L21/4763

CPC分类号： H01L21/76853 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76861 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

摘要翻译： 描述了半导体器件中的多层互连结构及其制造方法。 半导体器件中的多层互连结构包括形成在半导体晶片上的第一绝缘层，形成在第一绝缘层上的Cu互连层，形成在Cu互连层上的第二绝缘层和形成在界面处的金属氧化物层 在Cu互连层和第二绝缘层之间。 金属氧化物层通过在Cu互连层上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理而形成。

公开(公告)号：US11985814B2

公开(公告)日：2024-05-14

申请号：US17446445

申请日：2021-08-30

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Ning Xi ,  Peimeng Wang

IPC分类号： H10B12/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528

CPC分类号： H10B12/482 ,  H01L21/0206 ,  H01L21/76853 ,  H01L23/528 ,  H10B12/485

摘要： A method for manufacturing a bit line structure includes the following operations. A bit line conductive layer is formed on a surface of a semiconductor substrate, and the bit line conductive layer is partially located in a groove in the surface of the semiconductor substrate. A first protective layer is formed on surfaces of the bit line conductive layer and the semiconductor substrate. A first barrier layer is formed on a surface of the first protective layer. The surface of the first barrier layer is subjected with passivating treatment. A sacrificial layer is formed on the surface of the first barrier layer, and is provided with a filling part filled in the groove. A part, other than the filling part, of the sacrificial layer is cleaned and stripped.

公开(公告)号：US11694899B2

公开(公告)日：2023-07-04

申请号：US16896591

申请日：2020-06-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hsu Yang ,  Chun-Sheng Chen ,  Nai-Hao Yang ,  Kuan-Chia Chen ,  Huei-Wen Hsieh ,  Yu-Cheng Hsiao ,  Che-Wei Tien

IPC分类号： H01L21/285 ,  H01J37/34 ,  H01L21/768 ,  H01J37/32 ,  C23C14/18 ,  C23C14/34 ,  H01L21/321

CPC分类号： H01L21/28568 ,  C23C14/18 ,  C23C14/34 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/3426 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76853 ,  H01L21/76877 ,  H01L21/76882 ,  H01J2237/002 ,  H01J2237/332

摘要： Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

公开(公告)号：US20150325474A1

公开(公告)日：2015-11-12

申请号：US14793872

申请日：2015-07-08

申请人： President and Fellows of Harvard College

发明人： Roy Gerald GORDON ,  Harish B. BHANDARI ,  Yeung AU ,  Youbo LIN

IPC分类号： H01L21/768 ,  H01L21/288 ,  H01L21/285

CPC分类号： H01L23/53238 ,  C23C16/18 ,  C23C16/34 ,  C23C16/401 ,  H01L21/28506 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76853 ,  H01L21/76862 ,  H01L21/76867 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure for integrated circuits for copper wires in integrated circuits and methods for making the same are provided. Mn, Cr, or V containing layer forms a barrier against copper diffusing out of the wires, thereby protecting the insulator from premature breakdown, and protecting transistors from degradation by copper. The Mn, Cr, or V containing layer also promotes strong adhesion between copper and insulators, thus preserving the mechanical integrity of the devices during manufacture and use, as well as protecting against failure by electromigration of the copper during use of the devices and protecting the copper from corrosion by oxygen or water from its surroundings. In forming such integrated circuits, certain embodiments of the invention provide methods to selectively deposit Mn, Cr, V, or Co on the copper surfaces while reducing or even preventing deposition of Mn, Cr, V, or Co on insulator surfaces. Catalytic deposition of copper using a Mn, Cr, or V containing precursor and an iodine or bromine containing precursor is also provided.

摘要翻译： 提供了一种用于集成电路中铜线集成电路的互连结构及其制造方法。 含有Mn，Cr或V的层形成了阻碍铜从电线中扩散的阻挡层，从而保护绝缘体免于过早击穿，并保护晶体管免受铜的退化。 含Mn，Cr或V的层还促进了铜和绝缘体之间的强粘附，从而在制造和使用过程中保持了器件的机械完整性，并且在使用器件期间防止铜的电迁移失效，并保护 铜从其周围的氧气或水中腐蚀。 在形成这样的集成电路中，本发明的某些实施例提供了在铜表面上选择性地沉积Mn，Cr，V或Co的方法，同时减少或甚至防止在绝缘体表面上沉积Mn，Cr，V或Co。 还提供了使用含有Mn，Cr或V的前体和含碘或溴的前体的铜的催化沉积。

公开(公告)号：US20090236747A1

公开(公告)日：2009-09-24

申请号：US12382624

申请日：2009-03-19

申请人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

发明人： Junichi Koike ,  Yoshito Fujii ,  Jun Iijima ,  Noriyoshi Shimizu ,  Kazuyoshi Maekawa ,  Koji Arita ,  Ryotaro Yagi ,  Masaki Yoshimaru

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76853 ,  H01L21/288 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76861 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilevel interconnect structure in a semiconductor device comprises a first insulating layer (2) formed on a semiconductor wafer (1), a Cu interconnect layer (4) formed on the first insulating layer (2), a second insulating layer (6) formed on the Cu interconnect layer (4), and a metal oxide layer (5) formed at an interface between the Cu interconnect layer (4) and the second insulating layer (6). The metal oxide layer (5) is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer (4) and then heat-treating the plated layer in an oxidizing atmosphere.

摘要翻译： 半导体器件中的多层互连结构包括形成在半导体晶片（1）上的第一绝缘层（2），形成在第一绝缘层（2）上的Cu互连层（4），形成第二绝缘层（6） 在Cu互连层（4）上形成的金属氧化物层（5）形成在Cu互连层（4）与第二绝缘层（6）之间的界面处。 通过在Cu互连层（4）上浸渍诸如Sn或Zn的金属，然后在氧化气氛中对镀层进行热处理，形成金属氧化物层（5）。

公开(公告)号：US5981369A

公开(公告)日：1999-11-09

申请号：US865864

申请日：1997-05-30

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/76849 ,  H01L21/76853 ,  H01L27/10855 ,  H01L27/10894

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在半导体基板上淀积5​​00℃以下的温度。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US11798896B2

公开(公告)日：2023-10-24

申请号：US17344086

申请日：2021-06-10

申请人： AVX Corporation

发明人： Yehuda Seidman ,  Elinor O'Neill ,  Dan Rozbroj

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L23/64

CPC分类号： H01L23/562 ,  H01L21/76853 ,  H01L23/49805 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/64

摘要： A surface-mountable component is disclosed. The surface-mountable component may include a substrate having a side surface and a top surface that is perpendicular to the side surface. The component may include an element layer formed on the top surface of the substrate. The element layer may include a thin-film element and a contact pad electrically connected with the thin-film element. The contact pad may extend to the side surface of the substrate. The component may include a terminal that is electrically connected with the contact pad at a connection area. The connection area may be parallel with the top surface of the substrate. The terminal may have a visible edge surface that is approximately aligned with the side surface of the substrate. The visible edge surface may be visible for inspection when the surface-mountable component is mounted to a mounting surface.