公开(公告)号：US09793170B2

公开(公告)日：2017-10-17

申请号：US14856573

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/823475 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug adjacent to the first gate structure and contact the first spacer, and a first overhang feature disposed on an upper end of the first spacer.

公开(公告)号：US08598033B1

公开(公告)日：2013-12-03

申请号：US13646726

申请日：2012-10-07

Applicant: United Microelectronics Corp.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Bor-Shyang Liao ,  Chun-Ling Lin ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855

Abstract: The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.

Abstract translation: 本发明提供一种形成硅化物层的方法。 首先，在基板上形成含有金属原子的层，然后对含金属原子的层进行第一快速热处理（RTP），以在特定区域形成过渡型硅化物层。 然后除去含金属原子的层，在过渡型自对准硅化物层的表面上形成导热层，在过渡型硅化物层上进行第二层RTP。

公开(公告)号：US20170301670A1

公开(公告)日：2017-10-19

申请号：US15641336

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US09748233B2

公开(公告)日：2017-08-29

申请号：US14873223

申请日：2015-10-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

公开(公告)号：US09685316B2

公开(公告)日：2017-06-20

申请号：US13775273

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Kuo-Chih Lai ,  Chun-Ling Lin ,  Bor-Shyang Liao ,  Pin-Hong Chen ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/302 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/285

CPC classification number: H01L21/02063 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/76804 ,  H01L21/76814

Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.

公开(公告)号：US20160071800A1

公开(公告)日：2016-03-10

申请号：US14513230

申请日：2014-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Tsung-Hung Chang ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chia Chang Hsu ,  Hsin-Fu Huang ,  Chun-Yuan Wu ,  Shih-Fang Tzou

IPC: H01L23/535 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.

Abstract translation: 提供了包括电介质层，钛层，氮化钛层和金属的半导体结构。 电介质层设置在基板上，其中介电层具有通孔。 钛层覆盖通孔，其中钛层具有低于1500Mpa的拉伸应力。 氮化钛层共形地覆盖钛层。 金属填充通孔。 本发明还提供了一种用于形成所述半导体结构的半导体工艺。 半导体工艺包括以下步骤。 介电层形成在基板上，其中电介质具有通孔。 钛层保形地覆盖通孔，其中钛层具有低于500Mpa的压应力。 形成氮化钛层以保形地覆盖钛层。 金属填充通孔。

公开(公告)号：US20180012808A1

公开(公告)日：2018-01-11

申请号：US15697462

申请日：2017-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/823475 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device is provided. A substrate having a dummy gate thereon is prepared. A spacer is disposed on a sidewall of the dummy gate. A source/drain region is disposed adjacent to the dummy gate. A sacrificial layer is then formed on the source/drain region. A cap layer is then formed on the sacrificial layer. A top surface of the cap layer is coplanar with a top surface of the dummy gate. A replacement metal gate (RMG) process is performed to transform the dummy gate into a replacement metal gate. An opening is then formed in the cap layer to expose a top surface of the sacrificial layer. The sacrificial layer is removed through the opening, thereby forming a lower contact hole exposing a top surface of the source/drain region. A lower contact plug is then formed in the lower contact hole.

公开(公告)号：US20170236747A1

公开(公告)日：2017-08-17

申请号：US15586240

申请日：2017-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US09679813B2

公开(公告)日：2017-06-13

申请号：US14710583

申请日：2015-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Shu Min Huang ,  Min-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

公开(公告)号：US20170062416A1

公开(公告)日：2017-03-02

申请号：US14873223

申请日：2015-10-02

Applicant: United Microelectronics Corp.

Inventor： Chia Chang Hsu ,  Chun-Hsien Lin

IPC: H01L27/088 ,  H01L29/40 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/76819 ,  H01L21/76853 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/401 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the substrate to cover the gate structure entirely; planarizing the silicon layer; and performing a replacement metal gate (RMG) process to transform the gate structure into a metal gate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底; 在基板上形成硅层以完全覆盖栅极结构; 平坦化硅层; 并执行替换金属栅极（RMG）处理，以将栅极结构转换成金属栅极。