公开(公告)号：US12211888B2

公开(公告)日：2025-01-28

申请号：US17160319

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chi-Mao Hsu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Hsin-Fu Huang

IPC: H01C17/08 ,  H01C7/00 ,  H01L49/02

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

公开(公告)号：US09985110B2

公开(公告)日：2018-05-29

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09659937B2

公开(公告)日：2017-05-23

申请号：US14683128

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yun Chang ,  Chi-Mao Hsu ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

公开(公告)号：US09640482B1

公开(公告)日：2017-05-02

申请号：US15097301

申请日：2016-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Min-Chuan Tsai ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Yen-Tsai Yi ,  Wei-Chuan Tsai ,  Kuo-Chin Hung ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53266

Abstract: The present invention utilizes a barrier layer in the contact hole to react with an S/D region to form a silicide layer. After forming the silicide layer, a directional deposition process is performed to form a first metal layer primarily on the barrier layer at the bottom of the contact hole, so that very little or even no first metal layer is disposed on the barrier layer at the sidewall of the contact hole. Then, the second metal layer is deposited from bottom to top in the contact hole as the deposition rate of the second metal layer on the barrier layer is slower than the deposition rate of the second metal layer on the first metal layer.

公开(公告)号：US09478628B1

公开(公告)日：2016-10-25

申请号：US14853956

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Nien-Ting HO ,  Chi-Mao Hsu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Hsiang-Chieh Yen ,  Min-Chuan Tsai

IPC: H01L21/4763 ,  H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L29/66545

Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.

Abstract translation: 金属栅极形成工艺包括以下步骤。 第一金属层通过至少第一步骤和第二步骤形成在衬底上，其中第二步骤的处理能力高于第一步骤的处理能力。

公开(公告)号：US08598033B1

公开(公告)日：2013-12-03

申请号：US13646726

申请日：2012-10-07

Applicant: United Microelectronics Corp.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Bor-Shyang Liao ,  Chun-Ling Lin ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855

Abstract: The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.

Abstract translation: 本发明提供一种形成硅化物层的方法。 首先，在基板上形成含有金属原子的层，然后对含金属原子的层进行第一快速热处理（RTP），以在特定区域形成过渡型硅化物层。 然后除去含金属原子的层，在过渡型自对准硅化物层的表面上形成导热层，在过渡型硅化物层上进行第二层RTP。

公开(公告)号：US11139384B2

公开(公告)日：2021-10-05

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/43 ,  H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20200006514A1

公开(公告)日：2020-01-02

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20180331193A1

公开(公告)日：2018-11-15

申请号：US16044581

申请日：2018-07-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L29/49 ,  H01L29/06 ,  H01L27/092 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/42356 ,  H01L21/02183 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/518

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US20170323950A1

公开(公告)日：2017-11-09

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/285 ,  H01L29/267 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.