公开(公告)号：US10153231B2

公开(公告)日：2018-12-11

申请号：US15466847

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/285 ,  H01L21/768 ,  H01L23/532

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US20230238445A1

公开(公告)日：2023-07-27

申请号：US17676216

申请日：2022-02-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Chun-Chieh Chiu ,  Chun-Ling Lin ,  Shu Min Huang ,  Hsin-Fu Huang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L21/768 ,  H01L21/324

CPC classification number: H01L29/66431 ,  H01L29/2003 ,  H01L29/7786 ,  H01L21/76841 ,  H01L21/3245

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.

公开(公告)号：US20200168450A1

公开(公告)日：2020-05-28

申请号：US16203212

申请日：2018-11-28

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Kuan-Hsiang Chen ,  Hsin-Fu Huang ,  Chun-Ling Lin ,  Sheng-Yi Su ,  Pei-Hsun Kao

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: A method for fabricating interconnect of semiconductor device. The method includes providing a base substrate, having an inter-layer dielectric layer on top. A copper interconnect structure is formed in the inter-layer dielectric layer. A pre-sputter clean process is performed with hydrogen radicals on the copper interconnect structure. A degas process is sequentially performed on the copper interconnect structure. A cobalt cap layer is formed on the copper interconnect structure.

公开(公告)号：US20180138263A1

公开(公告)日：2018-05-17

申请号：US15350453

申请日：2016-11-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Yen-Chen Chen ,  Chin-Fu Lin ,  Chun-Yuan Wu ,  Chun-Ling Lin

IPC: H01L49/02

CPC classification number: H01L28/75

Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.

公开(公告)号：US20140242802A1

公开(公告)日：2014-08-28

申请号：US13775273

申请日：2013-02-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia Chang Hsu ,  Kuo-Chih Lai ,  Chun-Ling Lin ,  Bor-Shyang Liao ,  Pin-Hong Chen ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/02

CPC classification number: H01L21/02063 ,  H01L21/28518 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/6708 ,  H01L21/67109 ,  H01L21/76804 ,  H01L21/76814

Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.

Abstract translation: 半导体工艺包括以下步骤。 提供了基座上的晶片。 将基座抬起以接近加热源，并对晶片进行蚀刻处理。 通过加热源对晶片进行退火处理。 另一方面，提供了基座上的晶片和与基座在晶片相同侧的加热源。 通过将加热源和基座之间的温差设定为大于180℃，对晶片进行蚀刻处理。

公开(公告)号：US20190067184A1

公开(公告)日：2019-02-28

申请号：US16170059

申请日：2018-10-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76871 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US10079177B1

公开(公告)日：2018-09-18

申请号：US15694354

申请日：2017-09-01

Applicant: United Microelectronics Corp.

Inventor： Ko-Wei Lin ,  Ying-Lien Chen ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Hung-Miao Lin ,  Sheng-Yi Su ,  Tzu-Hao Liu

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L21/76873 ,  H01L21/28556 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76862 ,  H01L23/53238

Abstract: A method is provided for forming copper material over a substrate. The method includes forming a barrier layer over a substrate. Then, a depositing-soaking-treatment (DST) process is performed over the barrier layer. A copper layer is formed on the cobalt layer. The DST process includes depositing a cobalt layer on the barrier layer. Then, the cobalt layer is soaked with H2 gas at a first pressure. The cobalt layer is treated with a H2 plasma at a second pressure. The second pressure is lower than the first pressure.

公开(公告)号：US20180261537A1

公开(公告)日：2018-09-13

申请号：US15466847

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ko-Wei Lin ,  Hung-Miao Lin ,  Chun-Ling Lin ,  Ying-Lien Chen ,  Huei-Ru Tsai ,  Sheng-Yi Su

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/76871 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295

Abstract: An interconnect structure includes a dielectric layer and a conductor embedded in the dielectric layer. A top surface of the conductor is flush with a top surface of the dielectric layer. A cobalt cap layer is deposited on the top surface of the conductor. A nitrogen-doped cobalt layer is disposed on the cobalt cap layer.

公开(公告)号：US20150340280A1

公开(公告)日：2015-11-26

申请号：US14817227

申请日：2015-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Jia Chen ,  Chi-Mao Hsu ,  Tsun-Min Cheng ,  Chun-Ling Lin ,  Huei-Ru Tsai ,  Ching-Wei Hsu ,  Chin-Fu Lin ,  Hsin-Yu Chen

IPC: H01L21/768

CPC classification number: H01L21/76847 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via structure is located in a recess of a substrate. The through silicon via structure includes a barrier layer, a buffer layer and a conductive layer. The barrier layer covers a surface of the recess. The buffer layer covers the barrier layer. The conductive layer is located on the buffer layer and fills the recess, wherein the contact surface between the conductive layer and the buffer layer is smoother than the contact surface between the buffer layer and the barrier layer. Moreover, a through silicon via process forming said through silicon via structure is also provided.

Abstract translation: 硅通孔结构位于衬底的凹槽中。 贯通硅通孔结构包括阻挡层，缓冲层和导电层。 阻挡层覆盖凹部的表面。 缓冲层覆盖阻挡层。 导电层位于缓冲层上并填充凹槽，其中导电层和缓冲层之间的接触表面比缓冲层和阻挡层之间的接触表面更平滑。 此外，还提供了形成所述贯穿硅通孔结构的通硅通孔工艺。

公开(公告)号：US08598033B1

公开(公告)日：2013-12-03

申请号：US13646726

申请日：2012-10-07

Applicant: United Microelectronics Corp.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Bor-Shyang Liao ,  Chun-Ling Lin ,  Shu Min Huang ,  Min-Chung Cheng ,  Chi-Mao Hsu

IPC: H01L21/4763

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855

Abstract: The present invention provides a method for forming a salicide layer. First, a metal-atom-containing layer is formed on a substrate, a first rapid thermal process (RTP) is then performed to the metal-atom-containing layer to form a transitional salicide layer on a specific region. The metal-atom-containing layer is then removed, a thermal conductive layer is formed on the surface of the transitional salicide layer, and a second RTP is performed on the transitional salicide layer.

Abstract translation: 本发明提供一种形成硅化物层的方法。 首先，在基板上形成含有金属原子的层，然后对含金属原子的层进行第一快速热处理（RTP），以在特定区域形成过渡型硅化物层。 然后除去含金属原子的层，在过渡型自对准硅化物层的表面上形成导热层，在过渡型硅化物层上进行第二层RTP。