公开(公告)号：US20210217622A1

公开(公告)日：2021-07-15

申请号：US16896591

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsu Yang ,  Chun-Sheng Chen ,  Nai-Hao Yang ,  Kuan-Chia Chen ,  Huei-Wen Hsieh ,  Yu-Cheng Hsiao ,  Che-Wei Tien

IPC: H01L21/285 ,  H01J37/34 ,  H01L21/768 ,  H01L21/321 ,  H01J37/32 ,  C23C14/18 ,  C23C14/34

Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

公开(公告)号：US20240395617A1

公开(公告)日：2024-11-28

申请号：US18790994

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

公开(公告)号：US11694899B2

公开(公告)日：2023-07-04

申请号：US16896591

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsu Yang ,  Chun-Sheng Chen ,  Nai-Hao Yang ,  Kuan-Chia Chen ,  Huei-Wen Hsieh ,  Yu-Cheng Hsiao ,  Che-Wei Tien

IPC: H01L21/285 ,  H01J37/34 ,  H01L21/768 ,  H01J37/32 ,  C23C14/18 ,  C23C14/34 ,  H01L21/321

CPC classification number: H01L21/28568 ,  C23C14/18 ,  C23C14/34 ,  H01J37/3244 ,  H01J37/32633 ,  H01J37/3426 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76853 ,  H01L21/76877 ,  H01L21/76882 ,  H01J2237/002 ,  H01J2237/332

Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

公开(公告)号：US20240079270A1

公开(公告)日：2024-03-07

申请号：US18507759

申请日：2023-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76862 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L27/0886

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

公开(公告)号：US20230317459A1

公开(公告)日：2023-10-05

申请号：US18331321

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Chun-Hsu Yang ,  Huei-Wen Hsieh ,  Nai-Hao Yang ,  Yu-Cheng Hsiao ,  Chun-Sheng Chen ,  Che-Wei Tien ,  Kuan-Chia Chen

IPC: H01L21/285 ,  H01J37/34 ,  H01L21/768 ,  H01J37/32 ,  C23C14/18 ,  C23C14/34 ,  H01L21/321

CPC classification number: H01L21/28568 ,  H01J37/3426 ,  H01L21/76846 ,  H01L21/76882 ,  H01L21/7684 ,  H01J37/32633 ,  C23C14/18 ,  C23C14/34 ,  H01L21/3212 ,  H01J37/3244 ,  H01L21/76831 ,  H01L21/76853 ,  H01L21/76877 ,  H01J2237/332 ,  H01J2237/002

Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

公开(公告)号：US20210202310A1

公开(公告)日：2021-07-01

申请号：US17066706

申请日：2020-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

公开(公告)号：US11854878B2

公开(公告)日：2023-12-26

申请号：US17066706

申请日：2020-10-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088

CPC classification number: H01L21/76882 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76862 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L27/0886

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

公开(公告)号：US20220384255A1

公开(公告)日：2022-12-01

申请号：US17883965

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsu Yang ,  Chun-Sheng Chen ,  Nai-Hao Yang ,  Kuan-Chia Chen ,  Huei-Wen Hsieh ,  Yu-Cheng Hsiao ,  Che-Wei Tien

IPC: H01L21/768 ,  C23C14/34 ,  H01J37/32

Abstract: Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

公开(公告)号：US20220367265A1

公开(公告)日：2022-11-17

申请号：US17873941

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huei-Wen Hsieh ,  Kai-Shiang Kuo ,  Cheng-Hui Weng ,  Chun-Sheng Chen ,  Wen-Hsuan Chen

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.