公开(公告)号：US20240332419A1

公开(公告)日：2024-10-03

申请号：US18736207

申请日：2024-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Yu-Yun PENG ,  Keng-Chu LIN

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/308 ,  H01L21/76283 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L21/02145 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L29/7843

摘要： A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

公开(公告)号：US11664237B2

公开(公告)日：2023-05-30

申请号：US17121338

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chien-Hua Huang ,  Tzu-Hui Wei ,  Cherng-Shiaw Tsai

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/321

CPC分类号： H01L21/31144 ,  H01L21/02321 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/02142 ,  H01L21/02145 ,  H01L21/02148 ,  H01L21/02153 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/823475

摘要： An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US20180204721A1

公开(公告)日：2018-07-19

申请号：US15919902

申请日：2018-03-13

申请人： Applied Materials, Inc.

发明人： Feng Q. Liu ,  Ben-Li Sheu ,  David Knapp ,  David Thompson

IPC分类号： H01L21/02 ,  C23C16/18 ,  C23C16/34

CPC分类号： H01L21/02271 ,  C23C16/18 ,  C23C16/34 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L23/53238

摘要： Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are semiconductor devices and methods of making same with a barrier layer comprising Mn(N) and, optionally, an adhesion layer.

公开(公告)号：US09978882B2

公开(公告)日：2018-05-22

申请号：US15108554

申请日：2014-11-13

申请人： SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.

发明人： Shinichi Nagase ,  Atsushi Ogasawara ,  Koji Ito

IPC分类号： H01L21/67 ,  H01L29/861 ,  H01L21/762 ,  H01L21/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  C25D13/00

CPC分类号： H01L29/8613 ,  C25D13/00 ,  C25D13/02 ,  C25D13/12 ,  C25D13/22 ,  H01L21/02129 ,  H01L21/02142 ,  H01L21/02145 ,  H01L21/02161 ,  H01L21/02282 ,  H01L21/67126 ,  H01L21/76224 ,  H01L21/78 ,  H01L29/0649 ,  H01L29/66128 ,  H01L29/66136 ,  H01L29/8611

摘要： Provided is a method of manufacturing a semiconductor device according to the present invention, a ring-shaped electrode plate 18 with an opening having a diameter smaller than a diameter of a semiconductor wafer W is disposed between a first electrode plate 14 and a second electrode plate 16, the semiconductor wafer W is arranged between the ring-shaped electrode plate 18 and the second electrode plate 16, and a glass film is formed on a glass film forming scheduled surface in a state where a potential lower than a potential V2 of the second electrode plate 16 is applied to the ring-shaped electrode plate 18. According to the method of manufacturing a semiconductor device of the present invention, even when the glass film forming step is performed using the semiconductor wafer where the base insulating film is formed on the glass film forming scheduled surface as the semiconductor wafer, lowering of deposition efficiency of fine glass particles on the outer peripheral portion of the semiconductor wafer can be suppressed and hence, highly reliable semiconductor devices can be manufactured with high productivity.

公开(公告)号：US09893182B2

公开(公告)日：2018-02-13

申请号：US14989215

申请日：2016-01-06

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Yong Li

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7833 ,  H01L21/02142 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

摘要： The present disclosure provides a method for forming a field-effect fin transistor (FinFET) structure. The method includes providing a substrate with fin structures; forming a gate structures across the fin structures; and forming ion implantation regions in the fin structures at both sides of the gate structure. The method also includes removing top portions of the fin structures at both sides of the gate structure to form remaining portions of the fin structures; forming a first semiconductor material layer on the remaining portions of the fin structures; and forming a second semiconductor material layer on the first semiconductor material layer, the second semiconductor material being doped with barrier-lowering ions. The method further includes forming a metal layer on the second semiconductor material layer, and performing an annealing process on the metal layer to form a contact-resistance-reducing layer.

公开(公告)号：US20170141237A1

公开(公告)日：2017-05-18

申请号：US15349211

申请日：2016-11-11

申请人： Sadanori ARAE ,  Naoyuki UEDA ,  Yuki NAKAMURA ,  Yukiko ABE ,  Shinji MATSUMOTO ,  Yuji SONE ,  Ryoichi SAOTOME ,  Minehide KUSAYANAGI

发明人： Sadanori ARAE ,  Naoyuki UEDA ,  Yuki NAKAMURA ,  Yukiko ABE ,  Shinji MATSUMOTO ,  Yuji SONE ,  Ryoichi SAOTOME ,  Minehide KUSAYANAGI

IPC分类号： H01L29/786 ,  H01L21/4757 ,  H01L21/02 ,  H01L21/4763 ,  H01L27/12 ,  H01L29/66

CPC分类号： H01L29/78606 ,  G02F1/1368 ,  H01L21/02142 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869

摘要： A field-effect transistor includes a gate electrode, a source electrode and a drain electrode to take out electric current according to an application of a voltage to the gate electrode, a semiconductor layer disposed adjacent to the source electrode and the drain electrode, the semiconductor layer forming a channel between the source electrode and the drain electrode, a first insulating layer as gate insulating film disposed between the semiconductor layer and the gate electrode, and a second insulating layer covering at least a part of a surface of the semiconductor layer, the second insulating layer including an oxide including silicon and alkaline earth metal.

公开(公告)号：US09530691B1

公开(公告)日：2016-12-27

申请号：US15048280

申请日：2016-02-19

申请人： GLOBALFOUNDRIES INC.

发明人： Xunyuan Zhang ,  Errol Todd Ryan

IPC分类号： H01L21/8242 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/288 ,  H01L21/66 ,  H01L21/67

CPC分类号： H01L21/76897 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02255 ,  H01L21/288 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/67075 ,  H01L21/67098 ,  H01L21/67253 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

摘要： At least one method, apparatus and system disclosed herein for forming an integrated circuit having a dual-orientation self aligned via. A first dielectric layer is formed on a semiconductor substrate. At least one first metal feature is formed in a first metal layer. A first cap feature is deposited over the first metal feature. A manganese silicate etch stop layer is formed above the dielectric layer. An etch process is performed for removing for at least removing the first cap feature. A second metal feature is formed in a second metal layer. A dual-orientation self aligned via connecting a portion of the second metal feature to the first metal feature is formed.

摘要翻译： 本文公开的用于形成具有双向自对准通孔的集成电路的至少一种方法，装置和系统。 第一电介质层形成在半导体衬底上。 在第一金属层中形成至少一个第一金属特征。 第一盖特征被放置在第一金属特征上。 在电介质层上方形成硅酸铝蚀刻停止层。 执行蚀刻处理以移除以至少去除第一盖特征。 在第二金属层中形成第二金属特征。 形成通过将第二金属特征的一部分连接到第一金属特征的双向自对准。

公开(公告)号：US09496365B2

公开(公告)日：2016-11-15

申请号：US14458611

申请日：2014-08-13

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu

IPC分类号： H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/16 ,  H01L21/321

CPC分类号： H01L29/518 ,  H01L21/02142 ,  H01L21/02145 ,  H01L21/02156 ,  H01L21/02161 ,  H01L21/045 ,  H01L21/049 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/32105 ,  H01L29/1608 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66068 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/78684

摘要： A semiconductor device of an embodiment includes: an SiC layer; a gate insulating film provided on a surface of the SiC layer, the gate insulating film including an oxide film or an oxynitride film in contact with the surface of the SiC layer, the oxide film or the oxynitride film containing at least one element selected from B, Al, Ga (gallium), In, Sc, Y, La, Mg, Ca, Sr, and Ba, a concentration peak of the element in the gate insulating film being on the SiC side of the gate insulating film, the concentration peak of the element being in the oxide film or the oxynitride film, the gate insulating film having a region with a concentration of the element being not higher than 1×1016 cm−3 on the opposite side to the SiC layer with the concentration peak; and a gate electrode on the gate insulating film.

摘要翻译： 实施例的半导体器件包括：SiC层; 设置在所述SiC层的表面上的栅极绝缘膜，所述栅极绝缘膜包括与所述SiC层的表面接触的氧化膜或氧氮化物膜，所述氧化物膜或所述氧氮化物膜含有选自B的至少一种元素 ，Al，Ga（镓），In，Sc，Y，La，Mg，Ca，Sr和Ba中，栅极绝缘膜中元素的浓度峰位于栅极绝缘膜的SiC侧， 所述栅极绝缘膜具有在与具有浓度峰的SiC层相反的一侧的元素浓度不高于1×10 16 cm -3的区域; 以及栅极绝缘膜上的栅电极。

公开(公告)号：US20150014663A1

公开(公告)日：2015-01-15

申请号：US14329313

申请日：2014-07-11

申请人： KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

发明人： Soon Jong KWAK ,  Jae Ho JUN ,  Myung Suk LEE

IPC分类号： H01L51/52 ,  H01L51/56 ,  H01L27/32

CPC分类号： H01L21/02359 ,  H01L21/02126 ,  H01L21/02142 ,  H01L21/02172 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/0234 ,  H01L27/3244 ,  H01L51/5253

摘要： Provided is an organic light-emitting display apparatus including a hybrid protective film. The organic light-emitting display apparatus includes a substrate, a display unit disposed on the substrate and including an organic light-emitting device (OLED), and an encapsulation unit encapsulating the display unit and including the hybrid protective film. The hybrid protective film includes an inorganic part layer where carbon is removed, an organic part layer where carbon is contained in a predetermined amount, and a gradient part layer disposed between the inorganic part layer and the organic part layer and increasing an amount of carbon as being more contiguous to the organic part layer.

摘要翻译： 提供了包括混合保护膜的有机发光显示装置。 有机发光显示装置包括基板，设置在基板上并包括有机发光器件（OLED）的显示单元，以及封装显示单元并包括混合保护膜的封装单元。 混合保护膜包括除去碳的无机部分层，含有预定量的碳的有机部分层和设置在无机部分层和有机部分层之间的梯度部分层，并且将碳的量增加为 更接近有机部分层。

公开(公告)号：US20130041170A1

公开(公告)日：2013-02-14

申请号：US13569906

申请日：2012-08-08

申请人： Rajesh Odedra ,  Neil Boag ,  Jeff Anthis ,  Ravi Kanjolia ,  Mark Saly

发明人： Rajesh Odedra ,  Neil Boag ,  Jeff Anthis ,  Ravi Kanjolia ,  Mark Saly

IPC分类号： C07F13/00 ,  H01L21/02 ,  C23C16/44 ,  C23C16/40 ,  C23C16/50

CPC分类号： C07F13/00 ,  C23C16/18 ,  C23C16/40 ,  C23C16/45553 ,  H01L21/02142 ,  H01L21/02175 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/76841

摘要： Organometallic complexes and use thereof in thin film deposition, such as CVD and ALD are provided herein. The organometallic complexes are (alkyl-substituted η3-allyl)(carbonyl)metal complexes.

摘要翻译： 有机金属络合物及其在薄膜沉积中的应用，如CVD和ALD。 有机金属络合物是（烷基取代的和3-烯丙基）（羰基）金属络合物。