-
公开(公告)号:US20190103303A1
公开(公告)日:2019-04-04
申请号:US16158780
申请日:2018-10-12
申请人: ASM IP Holding B.V.
发明人: Han Wang , Qi Xie , Delphine Longrie , Jan Willem Maes , David de Roest , Julian Hsieh , Chiyu Zhu , Timo Asikainen , Krzysztof Kachel , Harald Profijt
IPC分类号: H01L21/768 , H01L21/02 , H01L21/311 , C23C16/00 , H01L23/532
CPC分类号: H01L21/7685 , C23C16/00 , C23C16/04 , C23C16/34 , C23C16/45527 , C23C16/56 , H01L21/02178 , H01L21/02205 , H01L21/02274 , H01L21/0228 , H01L21/02315 , H01L21/0234 , H01L21/31122 , H01L21/31144 , H01L21/76834 , H01L21/76897 , H01L23/53266
摘要: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
-
公开(公告)号:US09997405B2
公开(公告)日:2018-06-12
申请号:US14866621
申请日:2015-09-25
发明人: Anand Chandrashekar , Esther Jeng , Raashina Humayun , Michal Danek , Juwen Gao , Deqi Wang
IPC分类号: H01L21/44 , H01L21/768 , H01L21/285 , H01L21/321 , H01L21/324 , H01L27/11524 , H01L27/11556 , C23C16/00 , C23C16/04 , C23C16/50
CPC分类号: H01L21/76879 , C23C16/00 , C23C16/045 , C23C16/50 , H01L21/28556 , H01L21/321 , H01L21/324 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76898 , H01L27/11524 , H01L27/11556 , H01L2924/0002 , H01L2924/00
摘要: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.
-
公开(公告)号:US09887097B2
公开(公告)日:2018-02-06
申请号:US15163123
申请日:2016-05-24
发明人: Eric A. Hudson
IPC分类号: H01L21/311 , H01J37/32 , C23C16/50 , C23C16/52 , C23C16/455 , H01L21/3065 , C23C16/00 , C23C16/04 , H01L27/108
CPC分类号: H01L21/31138 , C23C16/00 , C23C16/045 , C23C16/45525 , C23C16/45544 , C23C16/50 , C23C16/52 , H01J37/32009 , H01J37/32091 , H01J37/32449 , H01J37/32899 , H01J2237/334 , H01L21/02118 , H01L21/0212 , H01L21/02271 , H01L21/0228 , H01L21/3065 , H01L21/31116 , H01L21/31144 , H01L27/1087
摘要: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reactants and/or reaction mechanisms that result in substantially complete sidewall coating at relatively low temperatures without the use of plasma. In some cases the protective coating is deposited using molecular layer deposition techniques. In certain implementations the protective coating is fluorinated.
-
公开(公告)号:US09805965B2
公开(公告)日:2017-10-31
申请号:US15395938
申请日:2016-12-30
CPC分类号: H01L21/28556 , C23C16/00 , G06K2009/00738 , H01J37/32697 , H01J37/32715 , H01J2237/334 , H01L21/02252 , H01L21/02274 , H01L21/0228 , H01L21/0262 , H01L21/265 , H01L21/3065 , H01L21/31116 , H01L21/31138 , H01L21/32136 , H01L21/67063 , H01L21/67103 , H01L21/6833 , H01L27/1255 , H01L29/93 , H04N7/181 , H04N7/188
摘要: Implementations described herein provide a chucking circuit for a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF coupling between an electrostatic chuck and a substrate placed thereon. In one embodiment, a chucking circuit for an electrostatic chuck (ESC) has one or more chucking electrodes disposed in a dielectric body of the ESC, a plurality of pixel electrodes disposed in the dielectric body, and a chucking circuit having the one or more chucking electrodes and the plurality of pixel electrodes, the chucking circuit operable to electrostatically chuck a substrate to a workpiece support surface of the ESC, the chucking circuit having a plurality of secondary circuits, wherein each secondary circuit includes at least one capacitor of a plurality of capacitors, each secondary circuit is configured to independently control an impedance between one of the pixel electrodes and a ground.
-
公开(公告)号:US09768577B2
公开(公告)日:2017-09-19
申请号:US14832833
申请日:2015-08-21
CPC分类号: H01S3/005 , C23C16/00 , G02B17/00 , G02B17/0848 , G02B27/00 , G02B27/108 , H01S3/00 , H01S3/10
摘要: A pulse multiplier includes a beam splitter and one or more mirrors. The beam splitter receives a series of input laser pulses and directs part of the energy of each pulse into a ring cavity. After circulating around the ring cavity, part of the pulse energy leaves the ring cavity through the beam splitter and part of the energy is recirculated. By selecting the ring cavity optical path length, the repetition rate of an output series of laser pulses can be made to be a multiple of the input repetition rate. The relative energies of the output pulses can be controlled by choosing the transmission and reflection coefficients of the beam splitter. This pulse multiplier can inexpensively reduce the peak power per pulse while increasing the number of pulses per second with minimal total power loss.
-
公开(公告)号:US09765455B2
公开(公告)日:2017-09-19
申请号:US14595294
申请日:2015-01-13
IPC分类号: D02J3/00 , C04B35/622 , C04B35/628 , D02J13/00 , C23C16/26 , C23C16/32 , C23C16/34 , C23C16/00 , C04B35/80 , C04B35/82 , D06L1/14 , F01D5/28 , F01D9/02 , F01D11/08
CPC分类号: D02J3/00 , C03C25/52 , C03C25/70 , C04B35/6286 , C04B35/62863 , C04B35/62868 , C04B35/62871 , C04B35/62873 , C04B35/62884 , C04B35/62894 , C04B35/80 , C04B35/82 , C04B2235/5224 , C04B2235/5228 , C04B2235/5236 , C04B2235/524 , C04B2235/5244 , C04B2235/5256 , C04B2235/5264 , C23C16/00 , C23C16/26 , C23C16/32 , C23C16/325 , C23C16/342 , C23C16/345 , D02J13/00 , D06L1/14 , F01D5/282 , F01D9/02 , F01D11/08 , F05D2220/32 , F05D2230/314 , F05D2230/90 , F05D2300/6033 , F05D2300/614
摘要: A method of preparing a fiber for use in forming a ceramic matrix composite material comprises the steps of removing a polymer coating from an outer surface of glass or ceramic fibers by providing heated and humidified gas across the glass or ceramic fibers for a period of time.
-
公开(公告)号:US09744694B2
公开(公告)日:2017-08-29
申请号:US14677575
申请日:2015-04-02
申请人: The Boeing Company
发明人: Thomas K. Tsotsis
CPC分类号: B29C33/40 , B29C33/02 , B29C33/3828 , B29C33/405 , B29K2883/00 , B29K2905/12 , B29K2995/0005 , C23C16/00 , C25D5/34 , C25D5/54 , C25D7/00
摘要: A tool including a tool body, the tool body including a substrate having a tool-side surface, an intermediate layer positioned over the tool-side surface, and an outer layer positioned over the intermediate layer, the outer layer including a metallic material.
-
公开(公告)号:US09637839B2
公开(公告)日:2017-05-02
申请号:US14193962
申请日:2014-02-28
发明人: Jing Kong , Lain-Jong Li , Yi-Hsien Lee
摘要: Aromatic molecules are seeded on a surface of a growth substrate; and a layer (e.g., a monolayer) of a metal dichalcogenide is grown via chemical vapor deposition on the growth substrate surface seeded with aromatic molecules. The seeded aromatic molecules are contacted with a solvent that releases the metal dichalcogenide layer from the growth substrate. The metal dichalcogenide layer can be released with an adhered transfer medium and can be deposited on a target substrate.
-
公开(公告)号:US20170095858A1
公开(公告)日:2017-04-06
申请号:US15286267
申请日:2016-10-05
发明人: Alexander STANKOWSKI , Roman ENGELI
IPC分类号: B22F1/02 , B22F9/04 , B22F1/00 , C23G5/00 , C23C14/08 , C23C16/30 , B33Y70/00 , B33Y10/00 , C23C16/44 , C23C16/32 , C23C16/40 , C23C16/34 , B22F9/16 , C23C14/06
CPC分类号: B22F1/02 , B22F1/0003 , B22F1/0081 , B22F1/0088 , B22F3/1055 , B22F9/04 , B22F9/16 , B22F2003/1059 , B22F2302/10 , B22F2302/15 , B22F2302/20 , B22F2302/25 , B22F2302/30 , B22F2302/45 , B22F2998/10 , B22F2999/00 , B33Y10/00 , B33Y70/00 , C23C14/0635 , C23C14/0641 , C23C14/0664 , C23C14/0676 , C23C14/08 , C23C16/308 , C23C16/32 , C23C16/34 , C23C16/40 , C23C16/4417 , C23G5/00 , Y02P10/24 , Y02P10/295 , B22F9/082 , C23C14/00 , C23C16/00 , B22F2201/11 , B22F2009/0824
摘要: Methods are disclosed for treating a base materials in a form of metallic powder made of super alloys based on Ni, Co, Fe or combinations thereof, or made of TiAl alloys, which treated powder can be used for additive manufacturing, such as for Selective Laser Melting of three-dimensional articles.
-
公开(公告)号:US20170088945A1
公开(公告)日:2017-03-30
申请号:US14870014
申请日:2015-09-30
发明人: Yu-Lun CHUEH , Henry MEDINA , Yu-Ze CHEN , Jian-Guang LI , Teng-Yu SU
IPC分类号: C23C16/30 , C23C16/52 , C23C16/505 , C23C16/448 , C23C14/34 , C23C16/02
CPC分类号: C23C14/08 , C23C14/083 , C23C14/5826 , C23C14/5866 , C23C16/00 , H01L21/00 , H01L31/00 , H01L35/00
摘要: A method of fabricating transition metal dichalcogenides includes a preparing step, a steaming step and a depositing step. The preparing step is performed for providing a transition metal substrate, a reactive gas and a solid chalcogenide. The steaming step is performed for heating the solid chalcogenide to generate a chalcogenide gas in a steaming space. The depositing step is performed for introducing the reactive gas into the chalcogenide gas to ionize the chalcogenide gas so as to generate a chalcogenide plasma in a depositing space. The depositing step is performed under a process vacuum pressure from low vacuum pressure to atmospheric pressure. The reactive gas and the chalcogenide gas are flowed from top to bottom through a top of the transition metal substrate. The loading substrate is heated at a loading substrate temperature, and the steaming space is different from the depositing space.
-
-
-
-
-
-
-
-
-