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12 条记录 (耗时 0.018 秒)

    Cross-point memory compensation
    2.
    发明授权
    Cross-point memory compensation 有权
    交叉点存储器补偿

    公开(公告)号：US09058857B2

    公开(公告)日：2015-06-16

    申请号：US13269717

    申请日：2011-10-10

    申请人： Zengtao T. Liu ,  Kirk D. Prall

    发明人： Zengtao T. Liu ,  Kirk D. Prall

    IPC分类号： G11C11/21 ,  G11C8/08 ,  G11C13/00

    CPC分类号： G11C13/004 ,  G11C8/08 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2013/0083 ,  G11C2213/77

    摘要： The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

    摘要翻译： 本文描述的设备和方法可以操作以测量所选择的接入线路和与存储器阵列的多个存储器单元的选定单元相关联的选择的感测线之间的电压差。 可以将电压差与为存储器操作指定的参考电压进行比较。 可以响应于比较来调整施加到用于存储器操作的所选单元的选择电压，例如动态地补偿寄生电压降。

    Methods of forming semiconductor constructions
    6.
    发明授权
    Methods of forming semiconductor constructions 有权
    形成半导体结构的方法

    公开(公告)号：US08551844B1

    公开(公告)日：2013-10-08

    申请号：US13480677

    申请日：2012-05-25

    申请人： Zengtao T. Liu

    发明人： Zengtao T. Liu

    IPC分类号： H01L21/336

    CPC分类号： H01L23/481 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/482 ,  H01L27/1052 ,  H01L27/10876 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include methods in which first insulative material is formed across a memory region and a peripheral region of a substrate. An etch stop structure is formed to have a higher portion over the memory region than over the peripheral region. A second insulative material is formed to protect the lower portion of the etch stop structure, and the higher portion is removed. Subsequently, at least some of the first and second insulative materials are removed. Some embodiments include semiconductor constructions having a first region with first features, and a second region with second features. The first features are closer spaced than the second features. A first insulative material is over the second region and an insulative structure is over the first insulative material. The structure has a stem joined to a bench. The bench has an upper surface, and the stem extends to above the upper surface.

    摘要翻译： 一些实施方案包括其中在衬底的存储区和外围区域形成第一绝缘材料的方法。 蚀刻停止结构形成为在存储区域上比在周边区域上具有更高的部分。 形成第二绝缘材料以保护蚀刻停止结构的下部，并且去除较高部分。 随后，去除第一和第二绝缘材料中的至少一些。 一些实施例包括具有具有第一特征的第一区域和具有第二特征的第二区域的半导体结构。 第一特征与第二特征相距更近。 第一绝缘材料在第二区域之上，绝缘结构超过第一绝缘材料。 该结构具有连接到工作台的杆。 工作台具有上表面，并且杆延伸到上表面上方。

    Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells
    7.
    发明授权
    Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells 有权
    存储单元的阵列和形成垂直层叠的存储单元阵列的方法

    公开(公告)号：US08933491B2

    公开(公告)日：2015-01-13

    申请号：US13074642

    申请日：2011-03-29

    申请人： Zengtao T. Liu

    发明人： Zengtao T. Liu

    IPC分类号： H01L23/52 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/249 ,  G11C13/0002 ,  G11C13/0011 ,  G11C2213/71 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

    摘要： An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.

    摘要翻译： 存储单元的垂直堆叠层的阵列包括存储器单元的各层内的多个水平定向的接入线以及层的高度向外的多个水平定向的全局感测线。 多个选择晶体管正在层级的内侧。 多对局部第一和第二垂直线延伸穿过层。 这些对中的单独的局部第一垂直线与全球感测线之一导电连接，并且与选择晶体管之一的两个源极/漏极区之一导电连接。 对中的单独的本地第二垂直线与一个选择晶体管的两个源极/漏极区域中的另一个导电连接。 存储单元的个体包括本地第二垂直线和其中一个水平访问线和其间的可编程材料的交叉的一个。 公开了包括方法的其他方面和实现。

    Methods of forming interconnects
    8.
    发明授权
    Methods of forming interconnects 有权
    形成互连的方法

    公开(公告)号：US08647977B2

    公开(公告)日：2014-02-11

    申请号：US13211601

    申请日：2011-08-17

    申请人： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

    发明人： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

    摘要翻译： 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

    Semiconductor Constructions and Methods of Forming Interconnects
    9.
    发明申请
    Semiconductor Constructions and Methods of Forming Interconnects 有权
    形成互连的半导体构造和方法

    公开(公告)号：US20130043597A1

    公开(公告)日：2013-02-21

    申请号：US13211601

    申请日：2011-08-17

    申请人： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

    发明人： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

    IPC分类号： H01L21/3205 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

    摘要翻译： 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。