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    Resistive memory and methods of processing resistive memory
    3.
    发明授权
    Resistive memory and methods of processing resistive memory 有权
    电阻记忆和处理电阻记忆的方法

    公开(公告)号：US08283198B2

    公开(公告)日：2012-10-09

    申请号：US12776764

    申请日：2010-05-10

    Applicant: David H. Wells

    Inventor： David H. Wells

    IPC: H01L21/00 ,  H01L29/08

    CPC classification number: H01L45/126 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/16

    Abstract: Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material.

    Abstract translation: 本文描述了电阻存储器和处理电阻性存储器的方法。 处理电阻性存储器的一个或多个方法实施例包括在具有存取装置接触的电极上形成电阻性存储单元材料，以及在电阻上形成电阻式存储单元材料之后，在电阻式存储单元材料上形成加热器电极，使得加热器 电极与电阻式存储单元材料自对准。

    CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY
    4.
    发明申请
    CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY 有权
    跨点存储器件，包括跨点存储器件的电子系统和在一个十字形存储器阵列中存取大量存储器单元的方法

    公开(公告)号：US20120182787A1

    公开(公告)日：2012-07-19

    申请号：US13430970

    申请日：2012-03-27

    Applicant: David H. Wells ,  Jun Liu

    Inventor： David H. Wells ,  Jun Liu

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

    Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

    NON-CONFORMAL MASKS, SEMICONDUCTOR DEVICE STRUCTURES INCLUDING THE SAME, AND METHODS
    5.
    发明申请
    NON-CONFORMAL MASKS, SEMICONDUCTOR DEVICE STRUCTURES INCLUDING THE SAME, AND METHODS 有权
    非一致性掩模，包括其的半导体器件结构和方法

    公开(公告)号：US20100308438A1

    公开(公告)日：2010-12-09

    申请号：US12477551

    申请日：2009-06-03

    Applicant: David H. Wells

    Inventor： David H. Wells

    IPC: H01L21/027 ,  H01L23/58

    CPC classification number: H01L21/3083 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76224

    Abstract: A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.

    Abstract translation: 一种制造半导体器件结构的方法包括在衬底的表面上形成非共形掩模。 在基板的表面上形成具有平面或基本平坦的上表面的非保形掩模材料。 非保形材料的平面度或实质平面度消除或基本上消除了在其上形成的“掩模”中的失真，并因此消除或基本上消除随后使用掩模图案形成的任何掩模中的畸变。 在一些实施例中，非保形掩模的掩模材料不延伸到衬底的上表面中的凹槽中; 而是“桥”了凹槽。 还公开了包括使用非保形掩模制造的非共形掩模和半导体器件结构的半导体器件结构。

    INTEGRATED CIRCUIT WITH BURIED DIGIT LINE
    6.
    发明申请
    INTEGRATED CIRCUIT WITH BURIED DIGIT LINE 有权
    集成电路与BURIED数字线

    公开(公告)号：US20100276741A1

    公开(公告)日：2010-11-04

    申请号：US12836404

    申请日：2010-07-14

    Applicant: David H. Wells

    Inventor： David H. Wells

    IPC: H01L27/108 ,  H01L29/78

    CPC classification number: H01L27/10808 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    Abstract: A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.

    Abstract translation: 公开了一种形成掩埋数字线的方法。 牺牲隔离物沿着隔离沟槽的侧壁形成，然后用牺牲材料填充。 一个间隔物被屏蔽，而另一个间隔物被去除，并且在去除的间隔物下方的衬底中的蚀刻步骤形成隔离窗。 然后，绝缘衬垫沿着排空的沟槽的侧壁形成，包括进入隔离窗。 然后在绝缘衬垫之间通过沟槽的底部形成数字线凹槽，这两个绝缘衬垫作为掩模加倍以自对准该蚀刻。 然后，数字线凹槽填充有金属和凹进的后部，并且具有可选的预先绝缘元件，并且沉积在凹部的底部中。

    Integrated Circuitry And Methods Of Forming A Semiconductor-On-Insulator Substrate
    7.
    发明申请
    Integrated Circuitry And Methods Of Forming A Semiconductor-On-Insulator Substrate 有权
    集成电路和形成半导体绝缘体衬底的方法

    公开(公告)号：US20100171176A1

    公开(公告)日：2010-07-08

    申请号：US12725797

    申请日：2010-03-17

    Applicant: David H. Wells

    Inventor： David H. Wells

    IPC: H01L23/34 ,  H01L29/786 ,  H01L21/336

    CPC classification number: H01L21/764 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/2015

    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

    Abstract translation: 一些实施例包括在半导体结构内形成空隙的方法。 在一些实施例中，空隙可以用作用于分配冷却剂的微结构，用于引导电磁辐射，或用于材料的分离和/或表征。 一些实施例包括其中具有对应于空隙，导管，绝缘结构，半导体结构或导电结构的微结构的结构。

    METHOD AND APPARATUS PROVIDING MULTI-PLANED ARRAY MEMORY DEVICE
    9.
    发明申请
    METHOD AND APPARATUS PROVIDING MULTI-PLANED ARRAY MEMORY DEVICE 有权
    提供多平面阵列存储器件的方法和装置

    公开(公告)号：US20090027938A1

    公开(公告)日：2009-01-29

    申请号：US11828092

    申请日：2007-07-25

    Applicant: David H. Wells

    Inventor： David H. Wells

    IPC: G11C5/02 ,  G11C11/00 ,  H01L21/06

    CPC classification number: H01L45/122 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/06

    Abstract: A three dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.

    Abstract translation: 三维可变电阻存储阵列及其形成方法。 存储器阵列具有三维的多个平面中的存储单元。 存储器单元的平面包括双重连接到驱动和感测电路的共享互连线，其用于寻址用于编程和读取的单元。 存储器阵列仅使用每个中心阵列平面的单个图案化掩模形成这样的平面的存储器单元。

    Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
    10.
    发明申请
    Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures 有权
    用于将音调乘以大于2的因子和相关的中间IC结构的单间隔处理

    公开(公告)号：US20080057692A1

    公开(公告)日：2008-03-06

    申请号：US11514117

    申请日：2006-08-30

    Applicant: David H. Wells ,  Mirzafer K. Abatchev

    Inventor： David H. Wells ,  Mirzafer K. Abatchev

    IPC: H01L21/44

    CPC classification number: H01L23/5386 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/942 ,  Y10S438/946 ,  Y10S438/947 ,  H01L2924/00

    Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n≧2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n−1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n−1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

    Abstract translation: 提供了用于将音调乘以大于2的因子的单间隔物处理。 在一个实施例中，n，其中n≥2，在衬底上形成层叠的心轴层，n层​​中的每一层包括基本上彼此平行的多个心轴。 层n上的心轴结束并平行于n-1层的心轴，层n的相邻心轴之间的距离大于n-1层相邻心轴之间的距离。 间隔件同时形成在心轴的侧壁上。 蚀刻掉心轴的裸露部分，并且由间隔物限定的线的图案被转移到基底。

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