Invention Application
- Patent Title: INTEGRATED CIRCUIT WITH BURIED DIGIT LINE
- Patent Title (中): 集成电路与BURIED数字线
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Application No.: US12836404Application Date: 2010-07-14
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Publication No.: US20100276741A1Publication Date: 2010-11-04
- Inventor: David H. Wells
- Applicant: David H. Wells
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/78

Abstract:
A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substrate beneath the removed spacer forms an isolation window. Insulating liners are then formed along the sidewalls of the emptied trench, including into the isolation window. A digit line recess is then formed through the bottom of the trench between the insulating liners, which double as masks to self-align this etch. The digit line recess is then filled with metal and recessed back, with an optional prior insulating element deposited and recessed back in the bottom of the recess.
Public/Granted literature
- US08102008B2 Integrated circuit with buried digit line Public/Granted day:2012-01-24
Information query
IPC分类: