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    Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array
    1.
    发明授权
    Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array 有权
    交叉点存储器件，包括交叉点存储器件的电子系统和访问交叉点存储器阵列中的多个存储器单元的方法

    公开(公告)号：US08144506B2

    公开(公告)日：2012-03-27

    申请号：US12489605

    申请日：2009-06-23

    Applicant: David H. Wells ,  Jun Liu

    Inventor： David H. Wells ,  Jun Liu

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

    Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

    Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array
    3.
    发明授权
    Cross-point memory devices, electronic systems including cross-point memory devices and methods of accessing a plurality of memory cells in a cross-point memory array 有权
    交叉点存储器件，包括交叉点存储器件的电子系统和访问交叉点存储器阵列中的多个存储器单元的方法

    公开(公告)号：US09025370B2

    公开(公告)日：2015-05-05

    申请号：US13430970

    申请日：2012-03-27

    Applicant: David H. Wells ,  Jun Liu

    Inventor： David H. Wells ,  Jun Liu

    IPC: G11C11/14 ,  G11C11/16 ,  G11C5/02 ,  G11C8/10

    CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

    Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

    CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY
    4.
    发明申请
    CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY 有权
    跨点存储器件，包括跨点存储器件的电子系统和在一个十字形存储器阵列中存取大量存储器单元的方法

    公开(公告)号：US20100321988A1

    公开(公告)日：2010-12-23

    申请号：US12489605

    申请日：2009-06-23

    Applicant: David H. Wells ,  Jun Liu

    Inventor： David H. Wells ,  Jun Liu

    IPC: G11C11/00 ,  G11C7/10 ,  G11C8/00

    CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

    Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

    METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY
    5.
    发明申请
    METHODS OF FORMING VERTICAL FIELD-EFFECT TRANSISTOR WITH SELF-ALIGNED CONTACTS FOR MEMORY DEVICES WITH PLANAR PERIPHERY/ARRAY AND INTERMEDIATE STRUCTURES FORMED THEREBY 有权
    用于具有平面外围/阵列的存储器件的自对准接触件形成垂直场效应晶体管的方法和形成的中间结构

    公开(公告)号：US20120248529A1

    公开(公告)日：2012-10-04

    申请号：US13078274

    申请日：2011-04-01

    Applicant: Jun Liu ,  Sanh D. Tang ,  David H. Wells

    Inventor： Jun Liu ,  Sanh D. Tang ,  David H. Wells

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L27/2454 ,  H01L21/823487 ,  H01L27/105 ,  H01L27/2463 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

    Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

    Abstract translation: 形成具有包括多个阵列晶体管的阵列部分和包括存储器件的外围电路晶体管结构的周边区域的存储器件的方法，其中外围区域的上表面和阵列部分的上表面是平面的（或 在形成外围电路晶体管结构和多个存储单元（形成在阵列晶体管上）之后，几乎是平面的）。 该方法包括在外围区域中形成外围电路晶体管结构，在阵列部分中形成多个阵列晶体管，并在各个垂直晶体管上形成多个存储单元。 通过该方法形成的结构具有外围和阵列区域的平面上表面。

    CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY
    6.
    发明申请
    CROSS-POINT MEMORY DEVICES, ELECTRONIC SYSTEMS INCLUDING CROSS-POINT MEMORY DEVICES AND METHODS OF ACCESSING A PLURALITY OF MEMORY CELLS IN A CROSS-POINT MEMORY ARRAY 有权
    跨点存储器件，包括跨点存储器件的电子系统和在一个十字形存储器阵列中存取大量存储器单元的方法

    公开(公告)号：US20120182787A1

    公开(公告)日：2012-07-19

    申请号：US13430970

    申请日：2012-03-27

    Applicant: David H. Wells ,  Jun Liu

    Inventor： David H. Wells ,  Jun Liu

    IPC: G11C11/00

    CPC classification number: G11C13/0069 ,  G11C5/02 ,  G11C8/10 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/004 ,  G11C2013/0054

    Abstract: Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

    Abstract translation: 存储器件包括多个存储器单元，每个存储器单元包括存储元件和选择器件。 多个第一（例如，行）地址线可以在多个的至少一些单元的第一侧相邻（例如，在下方）。 多个第二（例如，列）地址线跨越多个行地址线延伸，每个列地址线在至少一些单元的第二相对侧相邻（例如，在上）。 控制电路可以被配置为基本上同时向地址线施加读取电压或写入电压。 还公开了包括这种存储器件的系统和至少基本上同时访问多个单元的方法。

    Bed vacuum cleaner
    7.
    外观设计
    Bed vacuum cleaner 有权

    公开(公告)号：USD1025525S1

    公开(公告)日：2024-04-30

    申请号：US29850874

    申请日：2022-08-24

    Applicant: Jun Liu

    Designer： Jun Liu

    Abstract: FIG. 1 is a top perspective view of a bed vacuum cleaner, showing my new design;
    FIG. 2 is a bottom perspective view thereof;
    FIG. 3 is a front view thereof;
    FIG. 4 is a rear view thereof;
    FIG. 5 is a left side view thereof;
    FIG. 6 is a right side view thereof;
    FIG. 7 is a top view thereof; and,
    FIG. 8 is a bottom view thereof.
    It is mainly composed of HEPA Filter, high-frequency tapping, vacuum motor, and visual trash can. It combines three functions of purple light, polaroid and vacuuming to absorb particles such as hair, pollen, dust, dander, etc. it is suitable for cleaning beds, sofas and other fabric products.
    The broken lines in the drawings illustrate the portions of the bed vacuum cleaner, which form no part of the claimed design.

    Protein purification methods
    8.
    发明授权
    Protein purification methods 有权

    公开(公告)号：US10906934B2

    公开(公告)日：2021-02-02

    申请号：US14007610

    申请日：2012-03-23

    Applicant: Arick Brown ,  Junyan Ji ,  Jun Liu ,  Yuchang John Wang

    Inventor： Arick Brown ,  Junyan Ji ,  Jun Liu ,  Yuchang John Wang

    IPC: C07K1/34 ,  C12N7/00 ,  C07K16/00

    Abstract: The invention provides methods of reducing fouling of ultrafiltration membranes in processes wherein virus particles are removed from aqueous solutions comprising virus particles and at least one protein by adding a surfactant or non-surfactant, non-ionic agent to the aqueous solution prior to filtration. The invention also provides methods to dissociate protein aggregates or to reduce the formation of protein aggregates by adding a surfactant or non-surfactant, non-ionic agent to the protein solution.

    MARKERS ASSOCIATED WITH WNT INHIBITORS
    10.
    发明申请
    MARKERS ASSOCIATED WITH WNT INHIBITORS 有权
    与WNT抑制剂相关的标记

    公开(公告)号：US20160024587A1

    公开(公告)日：2016-01-28

    申请号：US14774212

    申请日：2014-03-10

    Applicant: Jianwei CHE ,  Jennifer HARRIS ,  Hsin-I HSIEH ,  Jie LI ,  Jun LIU ,  Nicholas NG

    Inventor： Jianwei Che ,  Jennifer Harris ,  Hsin-I Hsieh ,  Jie Li ,  Jun Liu ,  Nicholas Ng

    IPC: C12Q1/68 ,  A61K31/497

    Abstract: The invention provides methods of monitoring differential gene expression of biomarkers to determine patient sensitivity to Wnt inhibitor, methods of determining the sensitivity of a cell to an Wnt inhibitor by measuring biomarkers, methods of screening for candidate Wnt inhibitor, Wnt inhibitor for use in head and neck squamous cell carcinoma.

    Abstract translation: 本发明提供监测生物标志物的差异基因表达以确定患者对Wnt抑制剂的敏感性的方法，通过测量生物标志物来测定细胞对Wnt抑制剂的敏感性的方法，筛选候选Wnt抑制剂的方法，用于头部的Wnt抑制剂和 颈鳞状细胞癌。

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