公开(公告)号：US20090002706A1

公开(公告)日：2009-01-01

申请号：US11823107

申请日：2007-06-26

Applicant: Martin Weiss ,  Brian Kinnear ,  Telly Koffas ,  David Fryer ,  Ming-chuan Yang ,  William T. Blanton

Inventor： Martin Weiss ,  Brian Kinnear ,  Telly Koffas ,  David Fryer ,  Ming-chuan Yang ,  William T. Blanton

IPC: G01J4/00

CPC classification number: G03F9/7076 ,  G03F9/7065

Abstract: In one embodiment, a wafer alignment system, comprises a radiation source to generate radiation, a radiation directing assembly to direct at least a portion of the radiation onto a surface of a wafer, the radiation having a polarization state, an optical analyzer to collect at least a portion of the radiation reflected from the wafer, the wafer including at least a first region having a first grating pattern oriented in a first direction and at least a second region having a second grating pattern oriented in a second direction, different from the first direction.

Abstract translation: 在一个实施例中，晶片对准系统包括辐射源以产生辐射，辐射导向组件将辐射的至少一部分引导到晶片的表面上，所述辐射具有偏振状态，光学分析器收集在 从晶片反射的辐射的至少一部分，晶片至少包括具有沿第一方向取向的第一光栅图案的第一区域和至少第二区域，具有在第二方向上定向的第二光栅图案，第二区域不同于第一方向 方向。

公开(公告)号：US09177910B2

公开(公告)日：2015-11-03

申请号：US13449452

申请日：2012-04-18

Applicant: Tyler G. Hansen ,  Ming-Chuan Yang ,  Vishal Sipani

Inventor： Tyler G. Hansen ,  Ming-Chuan Yang ,  Vishal Sipani

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass.

Abstract translation: 用于集成电路的互连结构的实施例可以包括耦合到电路的第一导体，第二导​​体，第一和第二导体之间的电介质，以及在第一和第二导体之下并且耦合到第一和第二导体之下并在电介质之下通过的导电地下通道 或导电的立交桥，并且耦合到第一和第二导体并通过电介质。 第二导体将是浮动的，但是其与导电地下通道或导电立交桥的耦合。 在其它实施例中，可以包括可以使第二导体电隔离但是与导电地下通道或导电立交桥的耦合的另一电介质。

公开(公告)号：US20120278768A1

公开(公告)日：2012-11-01

申请号：US13098150

申请日：2011-04-29

Applicant: Ming-Chuan Yang ,  Jung H. Woo

Inventor： Ming-Chuan Yang ,  Jung H. Woo

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70125 ,  G03F7/70441 ,  G03F7/705

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract translation: 公开了用于诸如半导体制造的光刻工艺的掩模工艺变化性的随机模型的系统和方法。 在一个实施例中，随机误差模型可以基于掩模处理误差的概率分布。 随机误差模型可以产生具有随机误差的多个掩模布局，诸如接触的随机和非均匀变化。 在其他实施例中，随机模型可以应用于临界尺寸均匀性（CDU）优化或设计规则（DR）复杂度。

公开(公告)号：US20120244708A1

公开(公告)日：2012-09-27

申请号：US13491466

申请日：2012-06-07

Applicant: Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

Inventor： Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

IPC: H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract translation: 一些实施例包括形成开口的方法。 例如，结构可以具有多条导电线上的材料。 可以在材料上方形成多个环形特征，其中环形特征与线交叉。 图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。 环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

公开(公告)号：US08647977B2

公开(公告)日：2014-02-11

申请号：US13211601

申请日：2011-08-17

Applicant: Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

Inventor： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract translation: 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

公开(公告)号：US08389407B2

公开(公告)日：2013-03-05

申请号：US13491466

申请日：2012-06-07

Applicant: Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

Inventor： Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

IPC: H01L21/44

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract translation: 一些实施例包括形成开口的方法。 例如，结构可以具有多条导电线上的材料。 可以在材料上方形成多个环形特征，其中环形特征与线交叉。 图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。 环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

公开(公告)号：US20130043597A1

公开(公告)日：2013-02-21

申请号：US13211601

申请日：2011-08-17

Applicant: Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

Inventor： Ming-Chuan Yang ,  Zengtao T. Liu ,  Vishal Sipani

IPC: H01L21/3205 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.

Abstract translation: 一些实施例包括形成互连的方法。 可以形成第一电路电平，并且可以在这样的第一电平上形成第一电介质区域。 可以在第一介电区域上形成第二级别的电路。 可以形成互连以延伸穿过这样的第二级。 可以在第二电平层上形成第二电介质区域，并且可以在第二电介质区域上形成第三电平的电路。 第三级电路可以通过互连电连接到第一级电路。 一些实施例包括具有从电路的第一电平延伸通过第二电平电平的开口到第三电平电平的互连的结构; 具有包括多个单独的导电柱的单独互连。

公开(公告)号：US20120045896A1

公开(公告)日：2012-02-23

申请号：US12860765

申请日：2010-08-20

Applicant: Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

Inventor： Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

IPC: H01L21/768 ,  H01L21/302

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract translation: 一些实施例包括形成开口的方法。 例如，结构可以具有多条导电线上的材料。 可以在材料上方形成多个环形特征，其中环形特征与线交叉。 图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。 环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

公开(公告)号：US08715893B2

公开(公告)日：2014-05-06

申请号：US13615103

申请日：2012-09-13

Applicant: Ming-Chuan Yang

Inventor： Ming-Chuan Yang

IPC: G03F1/36 ,  G03C5/00

CPC classification number: G03F1/36

Abstract: Microlithography masks are disclosed, such as those that include one or more image reversal assist features disposed between at least two primary mask features. The one or more image reversal assist features may be defined by a patterned relatively non-transparent material on a mask substrate. Microlithography systems include such masks. Methods of forming microlithography masks are also disclosed, such as those that include patterning a relatively non-transparent material on a mask substrate to form at least one image reversal assist feature located between at least two primary features.

Abstract translation: 公开了微光刻掩模，例如包括设置在至少两个主掩模特征之间的一个或多个图像反转辅助特征的掩模。 一个或多个图像反转辅助特征可以由掩模基底上的图案化的相对不透明的材料限定。 微光刻系统包括这样的掩模。 还公开了形成微光刻掩模的方法，例如包括在掩模基板上图案化相对不透明的材料以形成位于至少两个主要特征之间的至少一个图像反转辅助特征的方法。

公开(公告)号：US08555210B2

公开(公告)日：2013-10-08

申请号：US13098150

申请日：2011-04-29

Applicant: Ming-Chuan Yang ,  Jung H. Woo

Inventor： Ming-Chuan Yang ,  Jung H. Woo

IPC: G06F17/50

CPC classification number: G06F17/50 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70125 ,  G03F7/70441 ,  G03F7/705

Abstract: Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

Abstract translation: 公开了用于诸如半导体制造的光刻工艺的掩模工艺变化性的随机模型的系统和方法。 在一个实施例中，随机误差模型可以基于掩模处理误差的概率分布。 随机误差模型可以产生具有随机误差的多个掩模布局，诸如接触的随机和非均匀变化。 在其他实施例中，随机模型可以应用于临界尺寸均匀性（CDU）优化或设计规则（DR）复杂度。