公开(公告)号：US12190958B2

公开(公告)日：2025-01-07

申请号：US17956225

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Sang Yong Yoon ,  Min Soo Kim ,  Jeong Hoon Nam ,  Hyeon Su Bak

IPC: G11C5/00 ,  G11C16/14 ,  G11C16/26

Abstract: A storage device and an operating method of the storage device are provided. The storage device comprises a first non-volatile memory device, a second non-volatile memory device, a third non-volatile memory device a storage controller configured to control the first non-volatile memory device, the second non-volatile memory device, and the third non-volatile memory device, control the first non-volatile memory device to extract a first on-cell count value after a first soft erase operation, set first to third read level offsets of the respective first to third non-volatile memory devices based on the respective first to third on-cell count values, select the first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and transmits first to third read commands based on the selected respective first to third defense code parameter sets to the respective first to third non-volatile memory devices.

公开(公告)号：US11923011B2

公开(公告)日：2024-03-05

申请号：US17837975

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Ho Seo ,  Suk-Eun Kang ,  Do Gyeong Lee ,  Ju Won Lee

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3404

Abstract: A storage device including a nonvolatile memory device that includes a nonvolatile memory cell array including a string including first and second memory cells stacked sequentially, and an OTP memory cell array that stores reference count values, the first and second memory cells respectively connected to first and second word lines; a controller including a processor that generates a read command for the first memory cell; a read level generator including a counter that receives the read command and calculates an off-cell count value of memory cells connected to the second word line, and a comparator that receives a first reference count value from the OTP memory cell array, compares the off-cell count value with the first reference count value to determine a threshold voltage shift of the second memory cell, and determines a read level of the first memory cell based on the threshold voltage shift.

公开(公告)号：US12020759B2

公开(公告)日：2024-06-25

申请号：US17878019

申请日：2022-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Juwon Lee ,  Suk-Eun Kang ,  Dogyeong Lee ,  Youngwook Jeong ,  Sang-Hyun Joo

IPC: G11C16/34 ,  G06N3/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G06N3/08 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/3495

Abstract: An operation method of a nonvolatile memory device includes performing a 1-stage program step and a 1-stage verify step on a first word line, storing a first time stamp, performing the 1-stage program step and the 1-stage verify step on a second word line, storing a second time stamp, calculating a delay time based on the first time stamp and the second time stamp, determining whether the delay time is greater than a threshold value, adjusting at least one 2-stage verify voltage associated with the first word line from a first voltage level to a second voltage level based on the delay time, and performing a 2-stage program step and a 2-stage verify step on the first word line. A level of the at least one 1-stage verify voltage is lower than the second voltage level, and the second voltage level is lower than the first voltage level.

公开(公告)号：US11715525B2

公开(公告)日：2023-08-01

申请号：US17408921

申请日：2021-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Yong-Lae Kim ,  Haneol Jang ,  Hyukje Kwon ,  Sang-Wan Nam

IPC: G11C16/10 ,  G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H10B43/27

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/10 ,  H10B43/27

Abstract: A nonvolatile memory device includes a memory block including a first structure formed on a substrate and a second structure formed on the first structure. An erase method of the nonvolatile memory device includes applying a word line erase voltage to first normal word lines of the first structure and second normal word lines of the second structure, and applying a junction word line erase voltage smaller than the word line erase voltage to at least one of a first junction word line of the first structure and a second junction word line of the second structure. The first junction word line is a word line adjacent to the second structure from among word lines of the first structure, and the second junction word line is a word line adjacent to the first structure from among word lines of the second structure.

公开(公告)号：US11942140B2

公开(公告)日：2024-03-26

申请号：US17958386

申请日：2022-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/10 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C11/4074 ,  G11C7/109 ,  G11C7/12 ,  G11C8/12 ,  G11C11/4082 ,  G11C11/4085 ,  G11C11/4097 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3436 ,  G11C2207/2209

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US11450389B2

公开(公告)日：2022-09-20

申请号：US17195824

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Ho Seo ,  Jung Ho Lee ,  Dae Sik Ham ,  Gi Baek Kim ,  Sang Yong Yoon ,  Won-Taeck Jung

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

Abstract: A non-volatile memory device including: a first string including a first string select transistor, a first memory cell and a first ground select transistor, a second string including a second string select transistor, a second memory cell and a second ground select transistor, and a controller to apply a pass voltage to a first string select line from a first time, apply a first read voltage to a first word line during a first read section from the first time to a second time, apply a first ground select line voltage to a first ground select line from the first time, apply a ground voltage to a second string select line, apply the first ground select line voltage to a second ground select line during a first control section, and apply a first common source line voltage to a common source line during the first control section.

公开(公告)号：US11017838B2

公开(公告)日：2021-05-25

申请号：US16991693

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee-Woong Kang ,  Dong-Hun Kwak ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

公开(公告)号：US10672454B2

公开(公告)日：2020-06-02

申请号：US16675331

申请日：2019-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C7/10 ,  G11C8/12 ,  G11C16/08 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US10777254B2

公开(公告)日：2020-09-15

申请号：US16817951

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Hun Kwak ,  Hee-Woong Kang ,  Jun-Ho Seo ,  Hee-Won Lee

IPC: G11C7/12 ,  G11C11/4074 ,  G11C16/30 ,  G11C16/10 ,  G11C16/06 ,  G11C16/04 ,  G11C11/56 ,  G11C11/4097 ,  G11C11/408 ,  G11C16/08 ,  G11C8/12 ,  G11C7/10 ,  G11C16/34

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a page buffer circuit, a row decoder and a control circuit. The memory cell array includes a plurality of mats corresponding to different bit-lines. The voltage generator generates word-line voltages applied to the memory cell array. The page buffer circuit is coupled to the memory cell array through bit-lines. The row decoder is coupled to the memory cell array through word-lines, and the row decoder transfers the word-line voltages to the memory cell array. The control circuit controls the voltage generator, the row decoder and the page buffer circuit based on a command and an address. The control circuit selects a voltage between different voltages to apply the selected different voltages to at least one of the word-lines or at least one of the bit-lines according to a number of mats of the plurality mats, which operate simultaneously.

公开(公告)号：US20160188772A1

公开(公告)日：2016-06-30

申请号：US14805606

申请日：2015-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Taek-Kyun Shin

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G06F17/5022 ,  G01R31/318583 ,  G06F17/5081

Abstract: In a method of and computing system for designing or modifying a design of an integrated circuit including a combinational logic and a scan chain, at least one flip-flop satisfying a predetermined condition is detected from among a plurality of flip-flops included in the scan chain by analyzing the combinational logic, and the detected flip-flop is replaced with a settable flip-flop that is set during a scan test for the integrated circuit, a resettable flip-flop that is reset during the scan test, or a settable-and-resettable flip-flop that is set or reset during the scan test.

Abstract translation: 在用于设计或修改包括组合逻辑和扫描链的集成电路的设计的方法和计算系统中，从包括在扫描中的多个触发器中检测满足预定条件的至少一个触发器 通过分析组合逻辑，并且检测到的触发器被替换为在集成电路的扫描测试期间设置的可设置触发器，在扫描测试期间被复位的可复位触发器，或可设置触发器， 和可复位触发器，在扫描测试期间设置或复位。