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公开(公告)号：US11450389B2
公开(公告)日：2022-09-20
申请号：US17195824
申请日：2021-03-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Seo , Jung Ho Lee , Dae Sik Ham , Gi Baek Kim , Sang Yong Yoon , Won-Taeck Jung
Abstract: A non-volatile memory device including: a first string including a first string select transistor, a first memory cell and a first ground select transistor, a second string including a second string select transistor, a second memory cell and a second ground select transistor, and a controller to apply a pass voltage to a first string select line from a first time, apply a first read voltage to a first word line during a first read section from the first time to a second time, apply a first ground select line voltage to a first ground select line from the first time, apply a ground voltage to a second string select line, apply the first ground select line voltage to a second ground select line during a first control section, and apply a first common source line voltage to a common source line during the first control section.
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公开(公告)号：US10720911B2
公开(公告)日：2020-07-21
申请号：US16521715
申请日：2019-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun Seok Shin , Jung Ho Lee , Michael Choi
Abstract: A bootstrap circuit including: a charge pump; a power unit including a bootstrap capacitor, wherein the bootstrap capacitor is charged using an output voltage of the charge pump; and a switch driver for generating a bootstrap signal based on a clock signal and an analog signal, wherein the analog signal is input to an analog switch, the switch driver for controlling the analog switch using the bootstrap signal, and including a first body switch connected between an input terminal and a body of the analog switch.
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公开(公告)号：US11012062B2
公开(公告)日：2021-05-18
申请号：US16933057
申请日：2020-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Eun Seok Shin , Jung Ho Lee , Michael Choi
Abstract: A bootstrap circuit including: a charge pump; a power unit including a bootstrap capacitor, wherein the bootstrap capacitor is charged using an output voltage of the charge pump; and a switch driver for generating a bootstrap signal based on a clock signal and an analog signal, wherein the analog signal is input to an analog switch, the switch driver for controlling the analog switch using the bootstrap signal, and including a first body switch connected between an input terminal and a body of the analog switch.
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公开(公告)号：US10104626B2
公开(公告)日：2018-10-16
申请号：US15365407
申请日：2016-11-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung Ho Lee , Yun Sung Mo , Ki Joon Hong , Young Seok Jung
Abstract: A method of processing a plurality of component carriers (CCs) included in a signal received by a user equipment includes receiving a first CC and a second CC, in which the first and second CCs have different reception timings, front-processing the first and second CCs asynchronously, controlling a timing between the first and second CCs using an alignment buffer memory, and processing the timing-controlled first and second CCs synchronously. The plurality of CCs includes at least the first and second CCs.
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公开(公告)号：US09723238B2
公开(公告)日：2017-08-01
申请号：US14730885
申请日：2015-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung Ho Lee , Hae Sick Sul , Sin Hwan Lim , Kyung Min Kim , Ho Jin Park , Jae Cheol Yun , Michael Choi
IPC: H04N5/335 , H04N5/378 , H04N5/369 , H04N5/3745
CPC classification number: H04N5/378 , H04N5/3698 , H04N5/3745
Abstract: An image processing device includes a switch signal generator, an amplifier, a ramp generator, and an attenuation control circuit. The switch signal generator generates switch control signals based on a level of an image signal that corresponds to a pixel signal output from a pixel. The amplifier includes a first input terminal and a second input terminal. The ramp generator generates a ramp signal. The attenuation control circuit adjusts an arrangement of capacitors according to the switch control signals to control whether to attenuate each of the pixel signal and the ramp signal, and transmits signals generated as a result of the adjusted arrangement to the first input terminal and the second input terminal.
