公开(公告)号：US11695668B2

公开(公告)日：2023-07-04

申请号：US17086206

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Rahul Khanna ,  Nishi Ahuja ,  Mrittika Ganguli

IPC: H04L43/08 ,  G06F16/901 ,  G06F1/18 ,  G06F1/20 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16 ,  G06F9/38 ,  G06F9/50 ,  H04L41/12 ,  H04L41/5019 ,  H04L43/16 ,  H04L47/24 ,  H04L47/38 ,  H04L67/1004 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H05K5/02 ,  H04W4/80 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  H04L43/065 ,  H04L61/00 ,  H04L67/51 ,  H04L41/147 ,  H04L67/1008 ,  H04L41/0813 ,  H04L67/1029 ,  H04L41/0896 ,  H04L47/70 ,  H04L47/78 ,  H04L41/082 ,  H04L67/00 ,  H04L67/1012 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L49/55 ,  H04L67/10 ,  H04W4/02 ,  H04L45/02 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L47/80 ,  H05K1/02 ,  H04L45/52 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L47/765 ,  H04L67/1014 ,  G06F12/10 ,  G06Q10/06 ,  G06Q10/0631 ,  G07C5/00 ,  H04L12/28 ,  H04L41/02 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L41/046 ,  H04L49/15

CPC classification number: H04L43/08 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G06F1/183 ,  G06F1/20 ,  G06F3/064 ,  G06F3/0613 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/30036 ,  G06F9/4401 ,  G06F9/544 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/1668 ,  G06F13/409 ,  G06F13/4022 ,  G06F13/4068 ,  G06F15/161 ,  G06F16/9014 ,  G08C17/02 ,  G11C5/02 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/3086 ,  H03M7/4056 ,  H03M7/4081 ,  H04B10/25891 ,  H04L41/145 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/0003 ,  H05K7/1442 ,  B25J15/0014 ,  B65G1/0492 ,  G05D23/1921 ,  G05D23/2039 ,  G06F3/061 ,  G06F3/067 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/0647 ,  G06F3/0658 ,  G06F3/0659 ,  G06F9/3887 ,  G06F9/505 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/5072 ,  G06F9/5077 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F13/161 ,  G06F13/1694 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C2200/00 ,  G11C5/06 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L41/024 ,  H04L41/046 ,  H04L41/082 ,  H04L41/0813 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/38 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/15 ,  H04L49/555 ,  H04L61/00 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/34 ,  H04L67/51 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0005 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y02D10/00 ,  Y02P90/30 ,  Y04S10/50 ,  Y04S10/52 ,  Y10S901/01

Abstract: Technologies for allocating resources of managed nodes to workloads to balance multiple resource allocation objectives include an orchestrator server to receive resource allocation objective data indicative of multiple resource allocation objectives to be satisfied. The orchestrator server is additionally to determine an initial assignment of a set of workloads among the managed nodes and receive telemetry data from the managed nodes. The orchestrator server is further to determine, as a function of the telemetry data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing an achievement of another of the resource allocation objectives, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed. Other embodiments are also described and claimed.

公开(公告)号：US20230062253A1

公开(公告)日：2023-03-02

申请号：US17883011

申请日：2022-08-08

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Stephen T. Palermo ,  Valerie J. Parker

IPC: H04L67/10 ,  H04L67/12

Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.

公开(公告)号：US11451455B2

公开(公告)日：2022-09-20

申请号：US16540800

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Arvind Srinivasan ,  Slawomir Putyrski ,  Donald E. Wood

IPC: H04L41/5009 ,  G06F13/28 ,  G06F15/173 ,  H04L12/06 ,  H04L41/5022 ,  H04L43/0852 ,  H04L49/9047 ,  H04L47/62 ,  H04L12/46 ,  H04L41/5003 ,  H04L47/6275

Abstract: Technologies for latency based service level agreement (SLA) management in remote direct memory access (RDMA) networks include multiple compute devices in communication via a network switch. A compute device determines a service level objective (SLO) indicative of a guaranteed maximum latency for a percentage of RDMA requests of an RDMA session. The compute device receives latency data indicative of latency of an RDMA request from a host device. The compute device determines a priority associated with the RDMA request as a function of the SLO and the latency data. The compute device schedules the RDMA request based on the priority. The network switch may allocate queue resources to the RDMA request based on the priority, reclaim the queue resources after the RDMA request is scheduled, and then return the queue resources to a free pool. Other embodiments are described and claimed.

公开(公告)号：US20220286399A1

公开(公告)日：2022-09-08

申请号：US17637416

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Niall McDonnell ,  Gage Eads ,  Mrittika Ganguli ,  Chetan Hiremath ,  John Mangan ,  Stephen Palermo ,  Bruce Richardson ,  Edwin Verplanke ,  Praveen Mosur ,  Bradley Chaddick ,  Abhishek Khade ,  Abhirupa Layek ,  Sarita Maini ,  Rahul Shah ,  Shrikant Shah ,  William Burroughs ,  David Sonnier

IPC: H04L47/125 ,  H04L47/625 ,  H04L47/62 ,  H04L47/6275

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

公开(公告)号：US11362904B2

公开(公告)日：2022-06-14

申请号：US16957626

申请日：2019-02-21

Applicant: INTEL CORPORATION

Inventor： Mrittika Ganguli ,  Dinesh Kumar ,  Robert Valiquette ,  Yadong Li ,  Mohan Kumar

IPC: H04L41/12 ,  H04L12/46

Abstract: Technologies for enhanced network discovery and configuration include a network with a fabric manager and multiple network devices. A network device requests platform information from a management controller and receives the platform information via a sideband interface. The network device broadcasts a discovery message indicative of the platform information on a link layer network. The fabric manager discovers the network topology with an enhanced link layer discovery protocol and creates a vPOD in the network. The vPOD includes an application network with multiple racks. The fabric manager creates a tagged network domain for the vPOD. The fabric manager sends an out-of-band configuration command to the network device with a tag associated with the vPOD. After receiving the out-of-band configuration command, the network device receives a packet, compares domain metadata of the packet to the tag received from the fabric manager, and routes the packet. Other embodiments are described and claimed.

公开(公告)号：US10735835B2

公开(公告)日：2020-08-04

申请号：US15395482

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Susanne M. Balle ,  Rahul Khanna ,  Nishi Ahuja ,  Mrittika Ganguli

IPC: G06F1/20 ,  G06F3/06 ,  H04L12/24 ,  H04L29/08 ,  G06F13/42 ,  H04Q11/00 ,  H05K7/14 ,  G06F9/50 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/931 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H03M7/30 ,  H05K13/04 ,  G06F13/16 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06F13/40 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933 ,  H04L12/947

Abstract: Technologies for allocating resources of a set of managed nodes to workloads to manage heat generation include an orchestrator server to receive resource allocation objective data including a target temperature for one or more of the managed nodes. The orchestrator server is also to determine an initial assignment of a set of workloads among the managed nodes, receive telemetry data from the managed nodes indicative of resource utilization by each of the managed nodes and one or more temperatures and fan speeds of the managed nodes as the workloads are performed, predict future heat generation of the workloads as a function of the telemetry data, determine, as a function of the predicted future heat generation, an adjustment to the assignment of the workloads to achieve the target temperature, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed.

公开(公告)号：US10721137B2

公开(公告)日：2020-07-21

申请号：US15198300

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Rahul Khanna ,  Ananth S. Narayan ,  Piyush Gupta

IPC: H04L12/24 ,  H04L29/08

Abstract: Systems described herein operate to improve network performance in a multi-tenant cloud computing environment. Systems can include communication circuitry and processing circuitry to generate a phase sequence matrix that indicates the identity and number of phases of a workload by measuring resources of the compute node during execution of the workload throughout a lifetime of the workload. The processing circuitry can generate a workload fingerprint that includes the phase sequence matrix and a phrase residency matrix. The phase residency matrix can indicate the fraction of execution time of the workload spent in each phase identified in the phase sequence matrix. A cloud controller can access the workload fingerprint for multiple workloads operating on multiple compute nodes in the cloud cluster to adjust workload allocations based at least on these workload fingerprints and on whether service level objectives (SLOs) are being met.

公开(公告)号：US10659386B2

公开(公告)日：2020-05-19

申请号：US15872928

申请日：2018-01-16

Applicant: Intel Corporation

Inventor： Subramony Sesha ,  Archana Patni ,  Ananth S. Narayan ,  Mrittika Ganguli

IPC: G06F15/173 ,  H04L12/911 ,  G06F9/50 ,  H04L29/08 ,  G06F9/455 ,  H04L12/26

Abstract: Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute node collects performance data indicative of cache contention on the compute node, for example, cache misses per thousand instructions. Each compute node determines a contention score as a function of the performance data and stores the contention score in a cloud state database. In response to a request for a new virtual machine, the cloud controller receives contention scores for the compute nodes and selects a compute node based on the contention score. The cloud controller schedules the new virtual machine on the selected compute node. The contention score may include a contention metric and a contention score level indicative of the contention metric. The contention score level may be determined by comparing the contention metric to a number of thresholds. Other embodiments are described and claimed.

公开(公告)号：US20190319892A1

公开(公告)日：2019-10-17

申请号：US16451454

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Anjaneya Reddy Chagam Reddy ,  Francesc Guim Bernat ,  Arvind Srinivasan

IPC: H04L12/873 ,  H04L12/911 ,  H04L12/875

Abstract: Technologies for managing burst bandwidth requirements are disclosed. In the illustrative embodiment, a software-defined network (SDN) controller monitors storage devices in a data center. If a storage device fails, the SDN controller manages the bandwidth used to replicate the data that was stored on the failed storage device. The SDN controller may allocate an initial amount of bandwidth based on one or more parameters of the storage device, and the SDN controller may increase the bandwidth in a series of discrete steps. In another embodiment, the SDN controller may predict a bandwidth burst based on sequential writes at a storage sled from several compute devices, and allocate bandwidth accordingly in a tiered manner.

公开(公告)号：US12197601B2

公开(公告)日：2025-01-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Somnath Paul ,  Yipeng Wang ,  Priya Autee ,  Abhirupa Layek ,  Shaman Narayana ,  Edwin Verplanke ,  Mrittika Ganguli ,  Jr-Shian Tsai ,  Anton Sorokin ,  Suvadeep Banerjee ,  Abhijit Davare ,  Desmond Kirkpatrick ,  Rajesh M. Sankaran ,  Jaykant B. Timbadiya ,  Sriram Kabisthalam Muthukumar ,  Narayan Ranganathan ,  Nalini Murari ,  Brinda Ganesh ,  Nilesh Jain

IPC: G06F15/78 ,  G06F9/50 ,  G06F21/62 ,  G06F21/72

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.