公开(公告)号：US12235761B2

公开(公告)日：2025-02-25

申请号：US16514226

申请日：2019-07-17

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Priya Autee ,  Abhishek Khade ,  Patrick Lu ,  Edwin Verplanke ,  Vivekananthan Sanjeepan

IPC: G06F12/0802

Abstract: Examples provide an application program interface or manner of negotiating locking or pinning or unlocking or unpinning of a cache region by which an application, software, or hardware. A cache region can be part of a level-1, level-2, lower or last level cache (LLC), or translation lookaside buffer (TLB) are locked (e.g., pinned) or unlocked (e.g., unpinned). A cache lock controller can respond to a request to lock or unlock a region of cache or TLB by indicating that the request is successful or not successful. If a request is not successful, the controller can provide feedback indicating one or more aspects of the request that are not permitted. The application, software, or hardware can submit another request, a modified request, based on the feedback to attempt to lock a portion of the cache or TLB.

公开(公告)号：US10178054B2

公开(公告)日：2019-01-08

申请号：US15088910

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Stephen T. Palermo ,  Iosif Gasparakis ,  Scott P. Dubal ,  Kapil Sood ,  Trevor Cooper ,  Jr-Shian Tsai ,  Jesse C. Brandeburg ,  Andrew J. Herdrich ,  Edwin Verplanke

IPC: H04L12/861 ,  H04L12/715 ,  H04L12/931 ,  G06F15/173

Abstract: Methods and apparatus for accelerating VM-to-VM Network Traffic using CPU cache. A virtual queue manager (VQM) manages data that is to be kept in VM-VM shared data buffers in CPU cache. The VQM stores a list of VM-VM allow entries identifying data transfers between VMs that may use VM-VM cache “fast-path” forwarding. Packets are sent from VMs to the VQM for forwarding to destination VMs. Indicia in the packets (e.g., in a tag or header) is inspected to determine whether a packet is to be forwarded via a VM-VM cache fast path or be forwarded via a virtual switch. The VQM determines the VM data already in the CPU cache domain while concurrently coordinating with the data to and from the external shared memory, and also ensures data coherency between data kept in cache and that which is kept in shared memory.

公开(公告)号：US20180373633A1

公开(公告)日：2018-12-27

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US10089229B2

公开(公告)日：2018-10-02

申请号：US15401220

申请日：2017-01-09

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Ravishankar Iyer ,  Christopher C. Gianos ,  Jeffrey D. Chamberlain ,  Ronak Singhal ,  Julius Mandelblat ,  Bret L. Toll

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

公开(公告)号：US12066939B2

公开(公告)日：2024-08-20

申请号：US17086243

申请日：2020-10-30

Applicant: Intel Corporation

Inventor： Rahul R. Shah ,  Omkar Maslekar ,  Priya Autee ,  Edwin Verplanke ,  Andrew J. Herdrich ,  Jeffrey D. Chamberlain

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F12/084 ,  G06F12/1009

Abstract: Examples described herein relate to a manner of demoting multiple cache lines to shared memory. In some examples, a shared cache is accessible by at least two processor cores and a region of the cache is larger than a cache line and is designated for demotion from the cache to the shared cache. In some examples, the cache line corresponds to a memory address in a region of memory. In some examples, an indication that the region of memory is associated with a cache line demote operation is provided in an indicator in a page table entry (PTE). In some examples, the indication that the region of memory is associated with a cache line demote operation is based on a command in an application executed by a processor. In some examples, the cache is an level 1 (L1) or level 2 (L2) cache.

公开(公告)号：US20240129353A1

公开(公告)日：2024-04-18

申请号：US18393236

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Amruta Misra ,  Niall McDonnell ,  Mrittika Ganguli ,  Edwin Verplanke ,  Stephen Palermo ,  Rahul Shah ,  Pushpendra Kumar ,  Vrinda Khirwadkar ,  Valerie Parker

IPC: H04L65/612 ,  H04L67/02 ,  H04L67/60

CPC classification number: H04L65/612 ,  H04L67/02 ,  H04L67/60

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.

公开(公告)号：US11650851B2

公开(公告)日：2023-05-16

申请号：US16678888

申请日：2019-11-08

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Christopher MacNamara ,  Sarita Maini ,  Abhishek Khade ,  Edwin Verplanke ,  Lokpraveen Mosur

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/505 ,  G06F9/45558 ,  G06F9/5044 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.

公开(公告)号：US10445271B2

公开(公告)日：2019-10-15

申请号：US14987676

申请日：2016-01-04

Applicant: Intel Corporation

Inventor： Ren Wang ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Yipeng Wang ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson

IPC: G06F13/37 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/0868 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20190004862A1

公开(公告)日：2019-01-03

申请号：US15637003

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Andrew J. Herdrich ,  Edwin Verplanke ,  Daniel Rivas Barragan

IPC: G06F9/50

Abstract: Technologies for managing quality of service of a platform interconnect include a compute device. The compute device includes one or more processors, one or more resources capable of being utilized by the one or more processors, and a platform interconnect to facilitate communication of messages between the one or more processors and the one or more resources. The compute device is to obtain class of service data for one or more workloads to be executed by the compute device. The class of service data is indicative of a capacity of one or more of the resources to be utilized in the execution of each corresponding workload. The compute device is also to execute the one or more workloads and manage the amount of traffic transmitted through the platform interconnect for each corresponding workload as a function of the class of service data as the one or more workloads are executed.

公开(公告)号：US20180352311A1

公开(公告)日：2018-12-06

申请号：US15913357

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Patrick L. Connor ,  Dinesh Kumar ,  Alexander W. Min ,  Daniel J. Dahle ,  Kapil Sood ,  Jeffrey B. Shaw ,  Edwin Verplanke ,  Scott P. Dubal ,  James Robert Hearn

IPC: H04Q9/02 ,  H04L12/26 ,  H04L12/24

CPC classification number: H04Q9/02 ,  H04L41/5009 ,  H04L41/5019 ,  H04L43/08 ,  H04L43/10

Abstract: Devices and techniques for out-of-band platform tuning and configuration are described herein. A device can include a telemetry interface to a telemetry collection system and a network interface to network adapter hardware. The device can receive platform telemetry metrics from the telemetry collection system, and network adapter silicon hardware statistics over the network interface, to gather collected statistics. The device can apply a heuristic algorithm using the collected statistics to determine processing core workloads generated by operation of a plurality of software systems communicatively coupled to the device. The device can provide a reconfiguration message to instruct at least one software system to switch operations to a different processing core, responsive to detecting an overload state on at least one processing core, based on the processing core workloads. Other embodiments are also described.