公开(公告)号：US11847008B2

公开(公告)日：2023-12-19

申请号：US15951391

申请日：2018-04-12

申请人： Intel Corporation

发明人： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

IPC分类号： G06F1/00 ,  G06F1/3228 ,  G06F1/3296 ,  G06F15/00 ,  G06F1/324

CPC分类号： G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F15/00

摘要： Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

公开(公告)号：US11641608B2

公开(公告)日：2023-05-02

申请号：US17184832

申请日：2021-02-25

申请人： Intel Corporation

发明人： Jonas Svennebring ,  Niall D. McDonnell ,  Andrey Chilikin ,  Andrew Cunningham ,  Christopher MacNamara ,  Carl-Oscar Montelius ,  Eliezer Tamir ,  Bjorn Topel

IPC分类号： H04W36/30 ,  H04W36/32 ,  H04L45/64 ,  H04W76/27 ,  H04L45/42 ,  H04W40/18 ,  H04W36/00 ,  H04W24/10 ,  H04L45/00 ,  H04L45/74

摘要： Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

公开(公告)号：US20220350676A1

公开(公告)日：2022-11-03

申请号：US17868391

申请日：2022-07-19

申请人： Intel Corporation

发明人： Eliezer Tamir ,  Johannes Berg ,  Andrew Cunningham ,  Peter Waskiewicz, JR. ,  Andrey Chilikin

IPC分类号： G06F9/50 ,  G06F9/48 ,  H04L69/22 ,  H04L47/10 ,  G06F9/4401 ,  H04L49/00 ,  H04L45/74 ,  H04L9/40

摘要： Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.

公开(公告)号：US10966135B2

公开(公告)日：2021-03-30

申请号：US16147220

申请日：2018-09-28

申请人： Intel Corporation

发明人： Jonas Svennebring ,  Niall D. McDonnell ,  Andrey Chilikin ,  Andrew Cunningham ,  Chris MacNamara ,  Carl-Oscar Montelius ,  Eliezer Tamir ,  Bjorn Topel

IPC分类号： H04W36/30 ,  H04W36/36 ,  H04L12/715 ,  H04W76/27 ,  H04L12/717 ,  H04W36/32 ,  H04W40/18 ,  H04W36/00 ,  H04W24/10 ,  H04L12/741

摘要： Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

公开(公告)号：US10754707B2

公开(公告)日：2020-08-25

申请号：US16058773

申请日：2018-08-08

申请人： Intel Corporation

发明人： Eliezer Tamir ,  Johannes Berg ,  Andrew Cunningham ,  Peter Waskiewicz, Jr. ,  Andrey Chilikin

IPC分类号： H04L29/06 ,  G06F9/50 ,  G06F9/48 ,  H04L12/815 ,  G06F9/4401 ,  H04L12/935 ,  H04L12/741

摘要： Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.

公开(公告)号：US10657056B2

公开(公告)日：2020-05-19

申请号：US16024773

申请日：2018-06-30

申请人： Intel Corporation

发明人： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

IPC分类号： G06F12/084 ,  G06F12/1072 ,  H04L12/933 ,  G06F12/128 ,  G06F13/28

摘要： Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

公开(公告)号：US12067427B2

公开(公告)日：2024-08-20

申请号：US17868391

申请日：2022-07-19

申请人： Intel Corporation

发明人： Eliezer Tamir ,  Johannes Berg ,  Andrew Cunningham ,  Peter Waskiewicz, Jr. ,  Andrey Chilikin

IPC分类号： G06F9/50 ,  G06F9/4401 ,  G06F9/48 ,  H04L9/40 ,  H04L45/74 ,  H04L47/10 ,  H04L49/00 ,  H04L69/22

CPC分类号： G06F9/5088 ,  G06F9/4411 ,  G06F9/4843 ,  G06F9/5027 ,  G06F9/5044 ,  H04L45/74 ,  H04L47/23 ,  H04L49/30 ,  H04L63/0209 ,  H04L63/0236 ,  H04L63/0245 ,  H04L69/22 ,  G06F2209/509

摘要： Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.

公开(公告)号：US11134021B2

公开(公告)日：2021-09-28

申请号：US15394488

申请日：2016-12-29

申请人： INTEL CORPORATION

发明人： Jonathan Kenny ,  Niall D. McDonnell ,  Andrew Cunningham ,  Debra Bernstein ,  William G. Burroughs ,  Hugh Wilkinson

IPC分类号： H04L12/863 ,  G06F13/00 ,  H04L12/801

摘要： Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

公开(公告)号：US11080202B2

公开(公告)日：2021-08-03

申请号：US15721800

申请日：2017-09-30

申请人： Intel Corporation

发明人： Niall D. McDonnell ,  Christopher MacNamara ,  John J. Browne ,  Andrew Cunningham ,  Brendan Ryan ,  Patrick Fleming ,  Namakkal N. Venkatesan ,  Bruce Richardson ,  Tomasz Kantecki ,  Sean Harte ,  Pierre Laurent

IPC分类号： G06F12/08 ,  G06F12/0888 ,  G06F12/0806 ,  G06F12/0817 ,  G06F12/0837 ,  G06F9/00

摘要： A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.

公开(公告)号：US10929323B2

公开(公告)日：2021-02-23

申请号：US16601137

申请日：2019-10-14

申请人： Intel Corporation

发明人： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC分类号： G06F13/37 ,  G06F9/54 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/04 ,  G06F9/38

摘要： Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.