知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

27 条记录 (耗时 0.019 秒)

    Technologies for network device flow lookup management
    2.
    发明授权
    Technologies for network device flow lookup management 有权

    公开(公告)号：US10284470B2

    公开(公告)日：2019-05-07

    申请号：US14580801

    申请日：2014-12-23

    申请人： Intel Corporation

    发明人： Ren Wang ,  Namakkal N. Venkatesan ,  Aamer Jaleel ,  Tsung-Yuan C. Tai ,  Sameh Gobriel ,  Christian Maciocco

    IPC分类号： H04L12/743 ,  H04L29/06 ,  H04L12/747

    摘要： Technologies for managing network flow lookups of a network device include a network controller and a target device, each communicatively coupled to the network device. The network device includes a cache for a processor of the network device and a main memory. The network device additionally includes a multi-level hash table having a first-level hash table stored in the cache of the network device and a second-level hash table stored in the main memory of the network device. The network device is configured to determine whether to store a network flow hash corresponding to a network flow indicating the target device in the first-level or second-level hash table based on a priority of the network flow provided to the network device by the network controller.

    Processors and methods for managing cache tiering with gather-scatter vector semantics
    3.
    发明授权
    Processors and methods for managing cache tiering with gather-scatter vector semantics 有权

    公开(公告)号：US10268580B2

    公开(公告)日：2019-04-23

    申请号：US15282483

    申请日：2016-09-30

    申请人： Intel Corporation

    发明人： Kshitij A. Doshi ,  Namakkal N. Venkatesan ,  Ren Wang ,  Andrew J. Herdrich

    IPC分类号： G06F9/30 ,  G06F12/128 ,  G06F12/0811

    摘要： Processors and methods implementing a machine instruction to perform cache line demotion on multiple cache lines to enable efficient sharing of cache lines between processor cores. One general aspect includes a processor comprising: a plurality of hardware processor cores, where each of the hardware processor cores to include a first cache. The processor also includes a second cache, communicatively coupled to and shared by the plurality of hardware processor cores. The processor to support a first machine instruction, the first machine instruction to include a vector register operand identifying a vector register which contains a plurality of data elements each used to identify a cache line. An execution of the first machine instruction by one of the plurality of hardware processor cores to cause a plurality of identified cache lines to be demoted, such that the demoted cache lines are moved from the first cache to the second cache.

    PACKET FLOW CLASSIFICATION
    4.
    发明申请
    PACKET FLOW CLASSIFICATION 审中-公开

    公开(公告)号：US20180103129A1

    公开(公告)日：2018-04-12

    申请号：US15677564

    申请日：2017-08-15

    申请人： Intel Corporation

    发明人： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

    IPC分类号： H04L29/06 ,  H04L12/743 ,  H04L12/64

    CPC分类号： H04L69/22 ,  H04L12/6418 ,  H04L45/7453

    摘要： Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.

    Techniques for flow control packet processing
    6.
    发明授权
    Techniques for flow control packet processing 有权

    公开(公告)号：US11418495B2

    公开(公告)日：2022-08-16

    申请号：US15715569

    申请日：2017-09-26

    申请人： INTEL CORPORATION

    发明人： John J. Browne ,  Chris Macnamara ,  Namakkal N. Venkatesan ,  Tomasz Kantecki ,  Declan W. Doherty

    IPC分类号： H04L29/06 ,  H04L9/40 ,  H04L47/10 ,  H04L69/166 ,  H04L47/2441 ,  H04L12/46

    摘要： Techniques and apparatuses for processing data unit are described. In one embodiment, for example, an apparatus for networking may include at least one memory, logic, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to access an encrypted packet having an encrypted portion, determine at least one flow control segment of the encrypted portion, decrypt the at least one flow control segment to generate a partially-decrypted packet comprising a decrypted at least one flow control segment and an encrypted remainder portion, the remainder portion comprising a portion of the encrypted packet that does not include the decrypted at least one flow control segment, access process information in the decrypted at least one flow control segment, and process the partially-decrypted packet according to the process information. Other embodiments are described and claimed.

    Packet flow classification
    7.
    发明授权
    Packet flow classification 有权

    公开(公告)号：US10455063B2

    公开(公告)日：2019-10-22

    申请号：US15677564

    申请日：2017-08-15

    申请人： Intel Corporation

    发明人： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

    IPC分类号： H04L29/06 ,  H04L12/743 ,  H04L12/64

    摘要： Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.