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    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING
    3.
    发明申请
    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING 有权

    公开(公告)号：US20220197851A1

    公开(公告)日：2022-06-23

    申请号：US17693696

    申请日：2022-03-14

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F15/173 ,  G06F11/14 ,  G06F9/48 ,  G06F15/76 ,  G06F11/30

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

    Systems and methods for multi-architecture computing
    4.
    发明授权
    Systems and methods for multi-architecture computing 有权

    公开(公告)号：US11275709B2

    公开(公告)日：2022-03-15

    申请号：US15584343

    申请日：2017-05-02

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F15/173 ,  G06F11/14 ,  G06F9/48 ,  G06F15/76 ,  G06F11/30 ,  H04L29/08 ,  G06F9/455 ,  H04L67/1001

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

    Active link during LAN interface reset
    5.
    发明授权
    Active link during LAN interface reset 有权

    公开(公告)号：US11134125B2

    公开(公告)日：2021-09-28

    申请号：US15749645

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Itamar Levin

    IPC: H04L12/851 ,  H04L29/06 ,  H04L29/08 ,  H04L12/24 ,  H04L12/861 ,  H04L12/835 ,  H04L12/825 ,  H04L12/28

    Abstract: Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one aspect, during normal operations traffic is transmitted over an Ethernet link coupling a first link partner to a second link partner. In response to a network interface re-configuration event, transmission of traffic over the Ethernet link is paused while keeping the Physical layer (PHY) of the Ethernet link active. The configuration of the first link partner is updated while the transmission of traffic is paused and the PHY of the Ethernet link is active. Upon completion of the configuration update, the link partners resume transmission of traffic over the Ethernet link. Additional schemes are provided that support re-configuration of network interfaces that support link and per priority flow control. According to another aspect, separate power domains are used for the PHY and the MAC circuitry, enabling the MAC circuitry to be reset via a power cycle while maintaining power to the PHY circuitry.

    System and method providing forward compatibility between a driver module and a network interface
    8.
    发明授权
    System and method providing forward compatibility between a driver module and a network interface 有权
    提供驱动程序模块和网络接口之间的前向兼容性的系统和方法

    公开(公告)号：US09256441B2

    公开(公告)日：2016-02-09

    申请号：US13659479

    申请日：2012-10-24

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Boris Kleiman ,  Ben-Zion Friedman ,  Eliel Louzoun

    IPC: H04L12/54 ,  G06F9/44

    CPC classification number: G06F9/4415

    Abstract: Generally, this disclosure provides systems and methods for providing forward compatibility between a driver module and one or more present or future versions of a network interface. The system may include a network interface configured to transfer data between a host system and a network; and a programmable circuit module associated with the network interface, the programmable circuit module configured to provide compatibility between the network interface and a driver module associated with the host system, wherein the driver module includes a first set of capabilities and the network interface includes a second set of capabilities.

    Abstract translation: 通常，本公开提供用于提供驱动器模块与网络接口的一个或多个当前版本或未来版本之间的前向兼容性的系统和方法。 该系统可以包括被配置为在主机系统和网络之间传送数据的网络接口; 以及与所述网络接口相关联的可编程电路模块，所述可编程电路模块被配置为提供所述网络接口和与所述主机系统相关联的驱动器模块之间的兼容性，其中所述驱动器模块包括第一组能力，并且所述网络接口包括第二 一套能力。

    PROVIDING, AT LEAST IN PART, AT LEAST ONE INDICATION THAT AT LEAST ONE PORTION OF DATA IS AVAILABLE FOR PROCESSING
    9.
    发明申请
    PROVIDING, AT LEAST IN PART, AT LEAST ONE INDICATION THAT AT LEAST ONE PORTION OF DATA IS AVAILABLE FOR PROCESSING 有权
    至少提供一些至少一个数据可供处理的指示

    公开(公告)号：US20150169325A1

    公开(公告)日：2015-06-18

    申请号：US14106253

    申请日：2013-12-13

    Applicant: Intel Corporation

    Inventor： Ygdal Naouri ,  Ronen Chayat ,  Ben-Zion Friedman ,  Parthasarathy Sarangam ,  Anil Vasudevan ,  Alain Gravel

    IPC: G06F9/30

    CPC classification number: H04L12/6418

    Abstract: An embodiment may include circuitry that may provide, at least in part, at least one indication that at least one portion of data is available for processing by at least one data processor. The at least one indication may be provided, at least in part, prior to the entirety of the at least one portion of the data being available for the processing by the at least one data processor. The at least one data processor may begin the processing in response, at least in part, to the at least one indication. Many alternatives, variations, and modifications are possible.

    Abstract translation: 一个实施例可以包括至少部分提供数据的至少一部分可供至少一个数据处理器进行处理的至少一个指示的电路。 该至少一个指示可以至少部分地在所述数据的至少一部分的整体可用于由所述至少一个数据处理器进行处理之前提供。 至少一个数据处理器可以至少部分地响应于至少一个指示来开始处理。 许多替代方案，变化和修改是可能的。

    FLOW CONTROL MECHANISM FOR A STORAGE SERVER
    10.
    发明申请
    FLOW CONTROL MECHANISM FOR A STORAGE SERVER 审中-公开
    存储服务器的流量控制机制

    公开(公告)号：US20140223026A1

    公开(公告)日：2014-08-07

    申请号：US13993525

    申请日：2012-01-10

    Applicant: INTEL CORPORATION

    Inventor： Eliezer Tamir ,  Phil C. Cayton ,  Ben-Zion Friedman ,  Robert O. Sharp ,  Donald E. Wood ,  Vadim Makhervaks

    IPC: H04L12/801

    CPC classification number: H04L47/39 ,  H04L67/1097

    Abstract: Generally, this disclosure relates to a method of flow control. The method may include determining a server load in response to a request from a client; selecting a type of credit based at least in part on server load; and sending a credit to the client based at least in part on server load, wherein server load corresponds to a utilization level of a server and wherein the credit corresponds to an amount of data that may be transferred between the server and the client and the credit is configured to decrease over time if the credit is unused by the client.

    Abstract translation: 通常，本公开涉及一种流量控制的方法。 该方法可以包括响应于来自客户端的请求来确定服务器负载; 至少部分地基于服务器负载选择一种类型的信用; 并且至少部分地基于服务器负载向客户端发送信用，其中服务器负载对应于服务器的利用水平，并且其中信用对应于可在服务器和客户端之间传送的数据量以及信用 如果客户端没有使用信用额，则配置为随时间减少。

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