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公开(公告)号:US11983131B2
公开(公告)日:2024-05-14
申请号:US17134361
申请日:2020-12-26
申请人: Intel Corporation
发明人: Patrick G. Kutch , Andrey Chilikin , Niall D. McDonnell , Brian A. Keating , Naveen Lakkakula , Ilango S. Ganga , Venkidesh Krishna Iyer , Patrick Fleming , Lokpraveen Mosur
IPC分类号: G06F13/40 , G06F3/06 , G06F9/50 , G06F12/0802 , G06F13/42
CPC分类号: G06F13/4027 , G06F3/0604 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F9/5083 , G06F12/0802 , G06F13/4221 , G06F2212/6042 , G06F2213/0026 , G06F2213/40
摘要: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
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公开(公告)号:US11539660B2
公开(公告)日:2022-12-27
申请号:US17222962
申请日:2021-04-05
申请人: Intel Corporation
IPC分类号: H04L61/2517 , H04L61/256 , H04L61/50
摘要: Examples include a computing system having a plurality of processing cores and a memory coupled to the plurality of processing cores. The memory has instructions stored thereon that, in response to execution by a selected one of the plurality of processing cores, cause the following actions. The selected processing core to receive a packet and get an original tuple from the packet. When no state information for a packet flow of the packet exists in a state table, select a new network address as a new source address for the packet, get a reverse tuple for a reverse direction, select a port for the packet from an entry in a mapping table based on a hash procedure using the reverse tuple, and save the new network address and selected port. Translate the packet's network address and port and transmit the packet.
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公开(公告)号:US20190097948A1
公开(公告)日:2019-03-28
申请号:US15718836
申请日:2017-09-28
申请人: Intel Corporation
发明人: John J. Browne , Christopher MacNamara , Tomasz Kantecki , Barak Hermesh , Sean Harte , Andrey Chilikin , Brendan Ryan , Bruce Richardson , Michael A. O'Hanlon , Andrew Cunningham
IPC分类号: H04L12/935 , H04L12/861
摘要: An apparatus, including: a hardware platform; logic to execute on the hardware platform, the logic configured to: receive a batch including first plurality of packets; identify a common attribute of the batch; perform batch processing on the batch according to the common attribute; generate a hint for the batch, the hint comprising information about the batch to facilitate processing of the batch; and forward the batch to a host platform network interface with the hint.
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公开(公告)号:US20190042326A1
公开(公告)日:2019-02-07
申请号:US16131008
申请日:2018-09-13
申请人: Intel Corporation
发明人: Andrey Chilikin , Sugesh Chandran
摘要: Technologies for the hierarchical clustering of hardware resources in network function virtualization (NFV) deployments include a compute node that is configured to create a network function profile that includes a plurality of network functions to be deployed on the compute node. Additionally, the compute node is configured to translate the network function profile usable to identify which of the plurality of network functions are to be managed by each of the plurality of interconnected hardware resources into a hardware profile for each of a plurality of interconnected hardware resources. The compute node is further configured to deploy each of the plurality of network functions to one or more of the plurality of interconnected hardware resources based on the hardware profile. Other embodiments are described herein.
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公开(公告)号:US20190007347A1
公开(公告)日:2019-01-03
申请号:US15637724
申请日:2017-06-29
申请人: Intel Corporation
IPC分类号: H04L12/861 , H04L12/935 , H04L12/863
摘要: Technologies for distributing network packet workload are disclosed. A compute device may receive a network packet and determine network packet extrinsic entropy information that is based on information that is not part of the contents of the network packet, such as an arrival time of the network packet. The compute device may use the extrinsic entropy information to assign the network packet to one of several packet processing queues. Since the assignment of network packets to the packet processing queues depend at least in part on extrinsic entropy information, similar or even identical packets will not necessarily be assigned to the same packet processing queue.
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公开(公告)号:US20190007320A1
公开(公告)日:2019-01-03
申请号:US15640465
申请日:2017-07-01
申请人: INTEL CORPORATION
IPC分类号: H04L12/803 , H04L12/721 , H04W24/02 , H04L12/46
摘要: Examples may include techniques to route packets to virtual network functions. A network function virtualization load balancer is provided which routes packets to both maximize a specified distribution and minimize switching of contexts between virtual network functions. Virtual network functions are arranged to be able to shift a context from one virtual network function to another. As such, the system can be managed, for example, scaled up or down, regardless of the statefullness of the virtual network functions and their local contexts or flows.
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公开(公告)号:US20180173547A1
公开(公告)日:2018-06-21
申请号:US15385561
申请日:2016-12-20
申请人: Intel Corporation
发明人: Ian Stokes , Andrey Chilikin
CPC分类号: G06F8/60 , G06F9/45558 , G06F2009/4557
摘要: A computer-implemented method can include a non-uniform memory access (NUMA) system deploying a virtual network function (VNF) to one or more cores of a first central processing unit (CPU) on a first socket of a host. The system can also include a Control Deployment Manager (CDM) for monitoring one or more data transmission metrics associated with the first socket. Responsive to the CDM determining that a more optimal configuration for the VNF may exist based on the monitored data transmission metric(s), the NUMA system can re-deploy the first VNF to at least one other core.
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公开(公告)号:US09952993B2
公开(公告)日:2018-04-24
申请号:US14499059
申请日:2014-09-26
申请人: Intel Corporation
发明人: Andrey Chilikin
IPC分类号: G06F13/36 , G06F13/362 , G06F13/364
CPC分类号: G06F13/3625 , G06F13/364 , Y02D10/14
摘要: The present disclosure pertains to a wired network which includes a master device and a plurality of slave devices coupled to the master device by a wired connection. The master device includes control logic to determine whether information is to be sent to a slave device. In addition, the master device includes a transmitter to drive a logic level for a predetermined amount of time to address the slave device in response to the control logic to determine whether information is to be sent to a slave device.
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公开(公告)号:US12067427B2
公开(公告)日:2024-08-20
申请号:US17868391
申请日:2022-07-19
申请人: Intel Corporation
CPC分类号: G06F9/5088 , G06F9/4411 , G06F9/4843 , G06F9/5027 , G06F9/5044 , H04L45/74 , H04L47/23 , H04L49/30 , H04L63/0209 , H04L63/0236 , H04L63/0245 , H04L69/22 , G06F2209/509
摘要: Examples include registering a device driver with an operating system, including registering available hardware offloads. The operating system receives a call to a hardware offload, inserts a binary filter representing the hardware offload into a hardware component and causes the execution of the binary filter by the hardware component when the hardware offload is available, and executes the binary filter in software when the hardware offload is not available.
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公开(公告)号:US12026116B2
公开(公告)日:2024-07-02
申请号:US17134361
申请日:2020-12-26
申请人: Intel Corporation
发明人: Patrick G. Kutch , Andrey Chilikin , Niall D. McDonnell , Brian A. Keating , Naveen Lakkakula , Ilango S. Ganga , Venkidesh Krishna Iyer , Patrick Fleming , Lokpraveen Mosur
IPC分类号: G06F13/40 , G06F3/06 , G06F9/50 , G06F12/0802 , G06F13/42
CPC分类号: G06F13/4027 , G06F3/0604 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F9/5083 , G06F12/0802 , G06F13/4221 , G06F2212/6042 , G06F2213/0026 , G06F2213/40
摘要: Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.
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