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    REORDERING OF DATA FOR PARALLEL PROCESSING
    2.
    发明申请
    REORDERING OF DATA FOR PARALLEL PROCESSING 审中-公开

    公开(公告)号：US20190097951A1

    公开(公告)日：2019-03-28

    申请号：US15719081

    申请日：2017-09-28

    申请人： Intel Corporation

    发明人： Tomasz Kantecki ,  Niall Power ,  John J. Browne ,  Christopher MacNamara ,  Stephen Doyle

    IPC分类号： H04L12/861 ,  H04L12/883

    摘要： A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

    TECHNOLOGIES FOR CACHE SIDE CHANNEL ATTACK DETECTION AND MITIGATION
    3.
    发明申请
    TECHNOLOGIES FOR CACHE SIDE CHANNEL ATTACK DETECTION AND MITIGATION 审中-公开

    公开(公告)号：US20190042739A1

    公开(公告)日：2019-02-07

    申请号：US16022976

    申请日：2018-06-29

    申请人： Intel Corporation

    发明人： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

    IPC分类号： G06F21/55 ,  G06F21/56

    摘要： Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

    Reordering of data for parallel processing
    6.
    发明授权
    Reordering of data for parallel processing 有权

    公开(公告)号：US11050682B2

    公开(公告)日：2021-06-29

    申请号：US15719081

    申请日：2017-09-28

    申请人： Intel Corporation

    发明人： Tomasz Kantecki ,  Niall Power ,  John J. Browne ,  Christopher MacNamara ,  Stephen Doyle

    IPC分类号： H04L12/861 ,  H04L12/883 ,  H04L12/801 ,  H04L12/935

    摘要： A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

    Technologies for demoting cache lines to shared cache
    7.
    发明授权
    Technologies for demoting cache lines to shared cache 有权

    公开(公告)号：US10657056B2

    公开(公告)日：2020-05-19

    申请号：US16024773

    申请日：2018-06-30

    申请人： Intel Corporation

    发明人： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC分类号： G06F12/084 ,  G06F12/1072 ,  H04L12/933 ,  G06F12/128 ,  G06F13/28

    摘要： Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

    Technologies for cache side channel attack detection and mitigation
    9.
    发明授权
    Technologies for cache side channel attack detection and mitigation 有权

    公开(公告)号：US10860714B2

    公开(公告)日：2020-12-08

    申请号：US16022976

    申请日：2018-06-29

    申请人： Intel Corporation

    发明人： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

    IPC分类号： G06F21/55 ,  G06F21/56

    摘要： Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    10.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    申请人： Intel Corporation

    发明人： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC分类号： G06F1/32

    摘要： Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.